Abstract: A large scale integrated circuit is designed to handle bus-to-bus data and address transfers, manipulation, and temporary storage. A key feature of the device is that it generates error correcting code parity bits on a byte wide basis so that ECC check bits for a multi-byte word can be generated externally with a minimum of hardware, and includes circuitry responsive to an error syndrome for correcting a single error within a byte. Data manipulation capabilities include standard logical operations, single bit shift operations, binary 2's complement arithmetic addition and subtraction, and decimal addition and subtraction. In addition, an input data byte on any bus can be passed unaltered or inverted to any other bus. The device is capable of receiving operands from one or two of three bidirectional data buses, performing a desired arithmetic or logical operation on the operand or operands, and returning the result to any one of the bidirectional buses including one which may have supplied one of the operands.

Abstract: An improved control system for a plurality of magnetic disc storage devices which connects one of said devices to a central processing unit for the transmission of data records to or from the central processing unit. The improvement comprises a unit logic controller connected to each disc storage device for receiving and storing priority control information and sector address information associated with a seek operation for a data record address. The unit logic controllers raise an alert signal when the data record address being sought is near the read-write head. The disc storage device having the highest priority associated with its alert signal is connected to the central processing unit for the transfer of data records by the control system. The improved control system requires that the central processing unit be connected to the disc storage device and the unit logic controller for the minimum amount of time during the process of locating a desired data record.