Patents by Inventor Edward E. Miller
Edward E. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9559694Abstract: In one embodiment, the operating range of an over-current detection circuit is extended to higher input voltage levels by providing a reference-voltage generation circuit for the detection circuit with voltage protection circuitry that applies an additional voltage drop to shield other vulnerable transistor devices from the higher input voltages. In addition, bypass circuitry is provided that is inactive at the highest input voltage levels, but actively bypasses at least some of the voltage protection circuitry at relatively low input voltage levels to apply a voltage drop that is sufficient to ensure proper operation of the vulnerable transistor devices at the low voltage levels. In one implementation, the vulnerable transistor devices are NFET devices in a programmable current mirror of the reference-voltage generation circuit. In addition, a stiffened voltage divider helps to ensure sufficient voltage drop at the low voltage levels. The protection and bypass circuitry also enable hot-socketing operations.Type: GrantFiled: July 22, 2013Date of Patent: January 31, 2017Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventor: Edward E. Miller
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Publication number: 20150022233Abstract: In one embodiment, the operating range of an over-current detection circuit is extended to higher input voltage levels by providing a reference-voltage generation circuit for the detection circuit with voltage protection circuitry that applies an additional voltage drop to shield other vulnerable transistor devices from the higher input voltages. In addition, bypass circuitry is provided that is inactive at the highest input voltage levels, but actively bypasses at least some of the voltage protection circuitry at relatively low input voltage levels to apply a voltage drop that is sufficient to ensure proper operation of the vulnerable transistor devices at the low voltage levels. In one implementation, the vulnerable transistor devices are NFET devices in a programmable current minor of the reference-voltage generation circuit. In addition, a stiffened voltage divider helps to ensure sufficient voltage drop at the low voltage levels. The protection and bypass circuitry also enable hot-socketing operations.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: Lattice Semiconductor CorporationInventor: Edward E. Miller
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Patent number: 8829944Abstract: In an integrated circuit having input circuitry whose positive and/or negative input signals are gated by one or more clocked input switches, the switch clock signal CLK_SW used to clock the input switch(es) is automatically generated based on the higher of the IC's power supply voltage VDD and the positive input signal voltage Vplus. In one embodiment, a clock level shifter shifts an input clock signal CLK_VDD from the VDD voltage domain to generate a level-shifted clock signal CLK_VPLUS in the Vplus voltage domain. Based on a control signal VSEL, a clock selector selects either the input clock signal or the level-shifted clock signal to be the switch clock signal. An over-voltage detector generates both the logic state and the voltage domain of the control signal based on the higher of VDD and Vplus, such that the input switches are appropriately clocked even during over-voltage conditions in which Vplus>VDD.Type: GrantFiled: September 30, 2013Date of Patent: September 9, 2014Assignee: Lattice Semiconductor CorporationInventor: Edward E. Miller
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Patent number: 7446573Abstract: In accordance with an embodiment of the present invention, a comparator system includes a plurality of multiplexers adapted to multiplex a number of differential input signals and a number of differential reference signals. A differencing circuit receives a differential input signal and a differential reference signal from the multiplexers and provides a differential output signal, which is used to provide a differential comparator output signal. A latch may be provided to perform differential-to-single ended conversion on the differential comparator output signal to provide a latch output signal. An output circuit may provide a registered digital output signal based on the latch output signal.Type: GrantFiled: February 24, 2006Date of Patent: November 4, 2008Assignee: Lattice Semiconductor CorporationInventor: Edward E. Miller
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Patent number: 7223827Abstract: A composition and a method of using the composition to adjust the permeability of a subsurface formation is disclosed. The composition is a water insoluble gel made by cross linking a water soluble polymer. The water soluble polymer is made by polymerizing a precursor composition, wherein the precursor composition is a mixture of an acrylic acid compound and a reactant comprised of a divalent metal salt of the acrylic acid compound.Type: GrantFiled: February 27, 2004Date of Patent: May 29, 2007Assignee: Fritz Industries, IncInventor: Edward E. Miller
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Patent number: 7056868Abstract: Water soluble associative polymers and compositions comprising them together with alkali metal salts of carboxylic acid are disclosed. Methods comprise introducing into a wellbore a fluid comprising such associative polymers and alkali metal salts of carboxylic acid, e.g., cesium formate. Disclosed water soluble associative polymers have functionality including at least sulfonate groups, carboxylate groups and hydrophobes associative with one another in a saturated aqueous solution of an alkali metal salt of a carboxylic acid.Type: GrantFiled: July 30, 2001Date of Patent: June 6, 2006Assignees: Cabot Corporation, Fritz Industries, Inc.Inventors: William J. Benton, Edward E. Miller, Neil Magri, John Toups
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Patent number: 7028201Abstract: A method and apparatus is provided to power-up a device having both digital and analog circuitry. The analog circuitry requires a stabilization period before proper operation. During power-up, the digital circuitry is held in reset by a power-on reset circuit. The power-on reset circuit releases the reset after the expiration of a power-on reset period. During the period of time after expiration of the power-on reset period and before the analog circuitry reaches equilibrium, the digital circuitry operates in a mode that does not require input signals from the analog circuitry. After the analog circuitry has reached equilibrium, the digital circuitry begins normal operation during which inputs signals from the analog circuitry may be processed by the digital circuitry.Type: GrantFiled: March 5, 2004Date of Patent: April 11, 2006Assignee: Lattice Semiconductor CorporationInventors: Douglas C. Morse, Edward E. Miller, Edward A. Ramsden
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Patent number: 7019584Abstract: A bandgap reference circuit can use various output stages to implement a controlled feedback method of sensing and supplying the needed load current through a sensing network. A small amount of circuitry can be added to a class AB output stage to decouple the bandgap reference feedback from a capacitive load and simultaneously sense load current needs and boost current as needed while minimizing voltage droop. Such circuits can be implemented using relatively compact designs while still reducing droop, and thus allowing the use of a large external capacitor to reduce noise and maintain good power supply rejection.Type: GrantFiled: January 30, 2004Date of Patent: March 28, 2006Assignee: Lattice Semiconductor CorporationInventors: Robert M. Bartel, Joey I. Doernberg, Edward E. Miller
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Patent number: 6970022Abstract: Comparator circuits, including rail-to-rail comparator circuits, can implement inverter structures such as current-starved inverters to provide hysteresis to the comparator's output. For example, a current-starved inverter can have its input driven by the comparator output and add current to the currents produced by the comparator's input stage. The inverter current can be derived from bias sources used to bias the input stage of the comparator so that the inverter current can track the input stage bias currents.Type: GrantFiled: September 18, 2003Date of Patent: November 29, 2005Assignee: Lattice Semiconductor CorporationInventor: Edward E. Miller
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Patent number: 6656989Abstract: Novel polymer compositions are disclosed, along with their use as well service fluids, for example as completion fluids, work-over fluids or drilling fluids, comprising water soluble copolymers having sulfonate groups and carboxylate groups, along with alkali metal salts of carboxylic acid. Exemplary copolymer has 5 to 95 wt. % structural units derived from 2-acrylamido-2-methylpropanesulfonic acid or salt thereof, and 5 to 95 wt. % structural units derived from acrylic acid or salt thereof. A salt of the polymer may be used, such as the sodium, potassium, ammonium and calcium salts. Exemplary alkali metal salts of the polymer composition include sodium, potassium and cesium salts of formic acid and/or acetic acid in amounts suitable to develop high temperature viscosity suitable for such well servicing fluids. The polymer composition is hydrateble/soluble in a brine of sodium and/or potassium and/or cesium salts of formic and/or acetic acid.Type: GrantFiled: May 19, 2000Date of Patent: December 2, 2003Assignees: Cabot Corporation, Fritz Industries, Inc.Inventors: William J. Benton, Edward E. Miller
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Publication number: 20030114317Abstract: Water soluble associative polymers and compositions comprising them together with alkali metal salts of carboxylic acid are disclosed. Methods comprise introducing into a wellbore a fluid comprising such associative polymers and alkali metal salts of carboxylic acid, e.g., cesium formate. Disclosed water soluble associative polymers have functionality including at least sulfonate groups, carboxylate groups and hydrophobes associative with one another in a saturated aqueous solution of an alkali metal salt of a carboxylic acid.Type: ApplicationFiled: July 30, 2001Publication date: June 19, 2003Inventors: William J. Benton, Edward E. Miller, Neil Magri, John Toups
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Patent number: 6420880Abstract: A semiconductor testing process effectively determines the integrity of a large capacitive structure buried within an integrated circuit. According to one example embodiment, a process of testing the oxide integrity of a circuit involves selecting a large gate oxide structure or structures that can be isolated from leakage paths. The dielectric integrity of the structure is tested by stressing the structure via voltage settings, comparable to a supply voltage, across its two terminals. The structure is connected to a current-sensitive node in-the integrated circuit across the two terminals. Other circuits connected to the current-sensitive node are shut off so that the current-sensitive node should be an island relative to other current paths. The leakage current at the current-sensitive node is then measured and compared with a reference level. From the measurements and comparison, a quality factor indicative of the dielectric integrity in the structure is determined.Type: GrantFiled: September 23, 1999Date of Patent: July 16, 2002Assignee: Koninklijke Philips Electronics N.V.Inventor: Edward E. Miller
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Patent number: 5065822Abstract: A process of profile modifying permeable soils with an environmentally safe composition of a non-toxic water-soluble polymer, a redox couple of a water-soluble ferrous salt and a non-toxic, oxidizing agent which are mixed in water and pumped into a subterranean formation wherein ferrous ion is oxidized to ferric ion to gel the polymer making the subterranean formation impermeable.Type: GrantFiled: September 14, 1990Date of Patent: November 19, 1991Assignee: American Cyanamid CompanyInventors: Edward E. Miller, Peter J. Strydom
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Patent number: 3931778Abstract: A machinery supporting arrangement suitable for use in maintenance and repair of dam walls comprising a barge with a liftable platform for carrying the machinery. The platform extends out over the top of a dam wall when the barge is moored alongside it so that the machinery becomes supported in part by the dam wall and in part by the barge.Type: GrantFiled: August 8, 1974Date of Patent: January 13, 1976Assignee: Raymond International, Inc.Inventors: Edward E. Miller, Eberhard V. Ranft