Abstract: A signal processor for use in a small, lightweight radar-guided missile to provide a discrete Fast Fourier Transform (FFT) on received radar return signals. The radar return signal are converted into a sequence of binary digits enabling a simple decoder to perform complex addition and subtraction processing, thereby minimizing the space and complexity of the signal processor.

Abstract: A digital signal processor adapted for use in small, lightweight radar-guided missiles. The processor includes a scratch pad register section, an arithmetic-logic unit and a control section arranged to enable data stored in two different storage elements included in such register section to be operated on by the arithmetic-logic unit, the result of such operation to be stored in a third storage element included in the register section and the contents stored in a program counter register to be incremented by one or jumped to a predetermined address selectively in accordance with the result of the arithmetic operation, all during the execution of a single one of a plurality of stored control instructions.

Abstract: A signal processor for use in a small, lightweight radar-guided missile to provide a discrete Fast Fourier Transform (FFT) on received radar return signals. The radar return signals are converted into a sequence of binary digits enabling a simple decoder to perform complex addition and subtraction processing, thereby minimizing the space and complexity of the signal processor.