Abstract: By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.

Abstract: By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.

Abstract: Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor and an asymmetric transistor on a substrate. A first mask is formed on the substrate with a first opening to enable implantation formation of first and second halo regions proximate first and second source/drain regions of the symmetric transistor. First and second halo regions of a first dosage are formed beneath the first gate by implanting off-axis through the first opening. A second mask is formed on the substrate with a second opening to enable implantation formation of a third halo region proximate a source region of the second asymmetric transistor while preventing formation of a halo region proximate a drain region of the asymmetric transistor. A third halo region of a second dosage greater than the first dosage is formed by implanting off-axis through the second opening.