Patents by Inventor Edward Engbrecht

Edward Engbrecht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9269607
    Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Edward Engbrecht, Donghun Kang, Rishikesh Krishnan, Oh-jung Kwon, Karen A. Nummy
  • Publication number: 20150364362
    Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Inventors: Edward Engbrecht, Donghun Kang, Rishikesh Krishnan, Oh-jung Kwon, Karen A. Nummy
  • Patent number: 8395228
    Abstract: A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Wu-Song Huang, Dario Leonardo Goldfarb, Martin Glodde, Edward Engbrecht, Yiheng Xu
  • Publication number: 20120112302
    Abstract: A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.
    Type: Application
    Filed: November 8, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wai-Kin Li, Wu-Song Huang, Dario Leonardo Goldfarb, Martin Glodde, Edward Engbrecht, Yiheng Xu
  • Publication number: 20070117371
    Abstract: A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.
    Type: Application
    Filed: November 23, 2005
    Publication date: May 24, 2007
    Inventors: Edward Engbrecht, Satyavolu Rao, Sameer Ajmera, Stephan Grunow
  • Publication number: 20060145398
    Abstract: The present invention pertains to disposing a diamond-like composition on a template, wherein the diamond-like composition acts as a release layer. The diamond-like composition is substantially transparent to actinic radiation, e.g., ultraviolet (UV) light, and will also have a desired surface energy, wherein the desired surface energy minimizes adhesion between the template and an underlying material disposed on a substrate. The diamond-like composition is characterized with a low surface energy that exhibits desirable release characteristics.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Todd Bailey, Nicholas Stacey, Edward Engbrecht, John Ekerdt