Abstract: An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.

Abstract: A power switching assembly includes a first driver circuit and a second driver circuit. The first driver circuit is supplied via a first internal supply node and a first reference node and drives a first gate signal. The second driver circuit is supplied via a second internal supply node and a second reference node and drives a second gate signal. The first gate signal and the second gate signal are configured to be in phase with each other. The first reference node and the second reference node are separated. A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

Abstract: An electronic device module includes: a core layer having an opening; an electronic device disposed in the opening, one or both of the core layer and the electronic device being at least partially covered by an adhesion promoter layer; and an encapsulant layer at least partially embedding the core layer and the electronic device.

Abstract: A method for fabricating a semiconductor device module includes: providing a first encapsulant layer and a core layer disposed on the first encapsulant layer, the core layer having an opening; disposing a semiconductor device in the opening, the semiconductor device having a die carrier and a semiconductor die disposed on the die carrier; dispensing an encapsulant onto the semiconductor device; applying a second polymer layer onto the encapsulant so that the encapsulant is pressed into the opening; and laminating together the first and second encapsulant layers and the encapsulant.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.

Abstract: A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

Abstract: A semiconductor package includes: a die carrier having a first main face and a second main face opposite to the first main face; a semiconductor die disposed on the die carrier, the semiconductor die including a first pad and a second pad; a first electrical connector disposed on the first pad; an encapsulant at least partially covering the semiconductor die, the die carrier, and the first electrical connector; and an insulation layer disposed on the second main face of the die carrier.

Abstract: A chip arrangement is provided. The chip arrangement may include a chip including a first main surface, wherein the first main surface includes an active area, a chip termination portion, and at least one contact pad. A first dielectric layer at least partially covers the chip termination portion and the active area, and at least partially exposes the at least one contact pad, and a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad.

Abstract: A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

Abstract: A semiconductor package includes a die pad comprising a die attach surface, a first lead extending away from the die pad, one or more semiconductor dies mounted on the die attach surface, the one or more semiconductor dies comprising first and second bond pads that each face away from the die attach surface, and a distribution element that provides a first transmission path for a first electrical signal between the first lead and the first bond pad of the one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and the second bond pad of the one or more semiconductor dies. The distribution element comprises at least one integrally formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths.

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

Abstract: A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.