Patents by Inventor Edward Fürgut

Edward Fürgut has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125218
    Abstract: An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heatsink.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Edward Fuergut, Peter Eibl, Horst Groeninger, Martin Gruber, Christian Kasztelan, Philipp Seng
  • Publication number: 20250118637
    Abstract: A carrier for carrying an electronic component of a package is disclosed. In one example, the carrier comprises a front side being provided with a horizontal component-sided area, and a back side opposing said front side and being provided with a horizontal back side area. A size of the horizontal back side area is larger than a size of the horizontal component-sided area.
    Type: Application
    Filed: September 12, 2024
    Publication date: April 10, 2025
    Applicant: Infineon Technologies AG
    Inventors: Lee Shuang WANG, Edward FÜRGUT, Arivindran NAVARETNASINGGAM
  • Patent number: 12261146
    Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: March 25, 2025
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Ralf Otremba, Irmgard Escher-Poeppel, Martin Gruber
  • Patent number: 12237242
    Abstract: A semiconductor device package comprises an electrically conductive carrier, a semiconductor die disposed on the carrier, an encapsulant encapsulating part of the carrier and the semiconductor die, an electrically insulating and thermally conductive interface structure, in particular covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant, wherein the interface structure comprises a glass transition temperature in a range between ?40° C. to 150° C.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: February 25, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Mayer, Edward Fuergut, Alexander Roth, Karina Rott
  • Patent number: 12218030
    Abstract: An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heat sink.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Peter Eibl, Horst Groeninger, Martin Gruber, Christian Kasztelan, Philipp Seng
  • Patent number: 12218029
    Abstract: A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: February 4, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Anton Mauder, Stephan Voss, Martin Gruber
  • Publication number: 20250038082
    Abstract: A package is disclosed. In one example, the package includes a carrier, an electronic component mounted on the carrier, an encapsulant fully encapsulating the electronic component and the carrier, electrically conductive leads electrically coupled with the carrier and/or with the electronic component and extending out of the encapsulant at opposing sides of the encapsulant, and a recess in at least one of two opposing main surfaces of the encapsulant and extending between two opposing further sides of the encapsulant. A difference between a creepage current path length including the recess and a further creepage current path is not more than 20%.
    Type: Application
    Filed: July 11, 2024
    Publication date: January 30, 2025
    Applicant: Infineon Technologies AG
    Inventors: Edward FÜRGUT, Dexter Inciong REYNOSO, Uwe SCHINDLER, Frank SINGER
  • Publication number: 20250022872
    Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
    Type: Application
    Filed: September 26, 2024
    Publication date: January 16, 2025
    Inventors: Edward Fuergut, Peter Friedrichs, Ralf Otremba, Hans-Joachim Schulze
  • Publication number: 20250014971
    Abstract: A semiconductor package includes an input side including input pins an output side including high voltage pins, an isolation structure that galvanically isolates the input side from the output side, an input driver die mounted on the input side and electrically connected with the input pins, first and second power transistor dies mounted on the output side and each having a first load terminal electrically connected with the high voltage pins, an output driver die that is communicatively coupled to the input driver die driver die via the isolation structure and is electrically connected with gate terminals of the first and second power transistor dies, and one or more electrically conductive structures forming a direct electrical connection between load terminals of the first and second power transistor dies, wherein the output driver die is mounted on one of the one or more electrically conductive structures.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: Richard Knipper, Frank Singer, Edward Fürgut, Dexter Inciong Reynoso
  • Publication number: 20240395646
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Infineon Technologies AG
    Inventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
  • Patent number: 12136623
    Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Peter Friedrichs, Ralf Otremba, Hans-Joachim Schulze
  • Patent number: 12125772
    Abstract: A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: October 22, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Herbert Hopfgartner, Bernd Schmoelzer
  • Publication number: 20240347427
    Abstract: A leadframe is disclosed. In one example, the leadframe comprises a die pad and a first lead comprising an inner portion and an external portion. The first lead comprises at least one elevation portion extending over a predetermined length in a longitudinal or lateral direction of the first lead. The external portion is configured to be used for external electrical connection. In another example, a semiconductor package having a leadframe is disclosed.
    Type: Application
    Filed: March 7, 2024
    Publication date: October 17, 2024
    Applicant: Infineon Technologies AG
    Inventors: Edward FÜRGUT, Teck Sim LEE, Guey Yong CHEE, Thai Kee GAN, Thomas BEMMERL, Markus FINK
  • Patent number: 12094793
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: September 17, 2024
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
  • Patent number: 12080669
    Abstract: A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: September 3, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Petteri Palm, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Publication number: 20240266237
    Abstract: A method for fabricating a semiconductor package includes: providing a die carrier; disposing a semiconductor die on the die carrier, the semiconductor die having one or more contact pads on a first main face thereof; applying an encapsulant at least partially to the semiconductor die, the encapsulant embedding at least one electrical connector, the electrical connector being connected with a contact pad or with the die carrier and extending to a main face of the encapsulant; and depositing at least one electrical layer onto the main face of the encapsulant and an exposed end of the at least one electrical connector.
    Type: Application
    Filed: January 25, 2024
    Publication date: August 8, 2024
    Inventors: Edward Fürgut, Thorsten Meyer, Wolfgang Scholz, Frank Zudock, Alexander Roth
  • Publication number: 20240250004
    Abstract: A method for fabricating a semiconductor device includes: providing a die carrier; disposing a semiconductor die on a main face of the die carrier, the semiconductor die having one or more contact pads; applying an encapsulant at least partially to the semiconductor die and at least a portion of the main face of the die carrier; applying an insulation layer to the encapsulant; and fabricating electrical interconnects by forming openings into the encapsulant and the insulation layer and filling a conductive material into the openings. Additional methods for fabricating a semiconductor device are described.
    Type: Application
    Filed: February 29, 2024
    Publication date: July 25, 2024
    Inventors: Edward Fuergut, Achim Althaus, Martin Gruber, Marco Nicolas Mueller, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas
  • Publication number: 20240243092
    Abstract: A semiconductor package includes: a leadframe having a die carrier and at least one first lead connected with the die carrier; a semiconductor transistor die connected with the die carrier and having a first surface and a second surface opposite to the first surface, a source pad disposed on the first surface, and a drain pad disposed on the second surface, the first surface facing a bottom side of the semiconductor package and the second surface facing a top side of the package; and a clip. The source pad is connected with the clip by at least one electrical connector.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 18, 2024
    Inventors: Edward Fürgut, Ralf Otremba, Julian Treu, Thai Kee Gan, Marcus Böhm
  • Publication number: 20240194566
    Abstract: An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Inventors: Edward Fuergut, Davide Chiola, Martin Gruber, Wolfram Hable
  • Patent number: 12002739
    Abstract: A semiconductor device includes a die carrier, a semiconductor die disposed on a main face of the die carrier, the semiconductor die including one or more contact pads, an encapsulant covering at least partially the semiconductor die and at least a portion of the main face of the die carrier, an insulation layer covering the encapsulant, and one or more electrical interconnects, each being connected with one of the one or more contact pads of the semiconductor die and extending through the encapsulant.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: June 4, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Achim Althaus, Martin Gruber, Marco Nicolas Mueller, Bernd Schmoelzer, Wolfgang Scholz, Mark Thomas