Abstract: A carrier for carrying an electronic component of a package is disclosed. In one example, the carrier comprises a front side being provided with a horizontal component-sided area, and a back side opposing said front side and being provided with a horizontal back side area. A size of the horizontal back side area is larger than a size of the horizontal component-sided area.

Abstract: A package is disclosed. In one example, the package includes a carrier, an electronic component mounted on the carrier, an encapsulant fully encapsulating the electronic component and the carrier, electrically conductive leads electrically coupled with the carrier and/or with the electronic component and extending out of the encapsulant at opposing sides of the encapsulant, and a recess in at least one of two opposing main surfaces of the encapsulant and extending between two opposing further sides of the encapsulant. A difference between a creepage current path length including the recess and a further creepage current path is not more than 20%.

Abstract: A semiconductor package includes an input side including input pins an output side including high voltage pins, an isolation structure that galvanically isolates the input side from the output side, an input driver die mounted on the input side and electrically connected with the input pins, first and second power transistor dies mounted on the output side and each having a first load terminal electrically connected with the high voltage pins, an output driver die that is communicatively coupled to the input driver die driver die via the isolation structure and is electrically connected with gate terminals of the first and second power transistor dies, and one or more electrically conductive structures forming a direct electrical connection between load terminals of the first and second power transistor dies, wherein the output driver die is mounted on one of the one or more electrically conductive structures.

Abstract: A leadframe is disclosed. In one example, the leadframe comprises a die pad and a first lead comprising an inner portion and an external portion. The first lead comprises at least one elevation portion extending over a predetermined length in a longitudinal or lateral direction of the first lead. The external portion is configured to be used for external electrical connection. In another example, a semiconductor package having a leadframe is disclosed.

Abstract: A method for fabricating a semiconductor package includes: providing a die carrier; disposing a semiconductor die on the die carrier, the semiconductor die having one or more contact pads on a first main face thereof; applying an encapsulant at least partially to the semiconductor die, the encapsulant embedding at least one electrical connector, the electrical connector being connected with a contact pad or with the die carrier and extending to a main face of the encapsulant; and depositing at least one electrical layer onto the main face of the encapsulant and an exposed end of the at least one electrical connector.

Abstract: A semiconductor package includes: a leadframe having a die carrier and at least one first lead connected with the die carrier; a semiconductor transistor die connected with the die carrier and having a first surface and a second surface opposite to the first surface, a source pad disposed on the first surface, and a drain pad disposed on the second surface, the first surface facing a bottom side of the semiconductor package and the second surface facing a top side of the package; and a clip. The source pad is connected with the clip by at least one electrical connector.

Abstract: A power switching assembly includes a first driver circuit and a second driver circuit. The first driver circuit is supplied via a first internal supply node and a first reference node and drives a first gate signal. The second driver circuit is supplied via a second internal supply node and a second reference node and drives a second gate signal. The first gate signal and the second gate signal are configured to be in phase with each other. The first reference node and the second reference node are separated. A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

Abstract: A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.

Abstract: An electronic device module includes: a core layer having an opening; an electronic device disposed in the opening, one or both of the core layer and the electronic device being at least partially covered by an adhesion promoter layer; and an encapsulant layer at least partially embedding the core layer and the electronic device.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.

Abstract: A method for fabricating a semiconductor device module includes: providing a first encapsulant layer and a core layer disposed on the first encapsulant layer, the core layer having an opening; disposing a semiconductor device in the opening, the semiconductor device having a die carrier and a semiconductor die disposed on the die carrier; dispensing an encapsulant onto the semiconductor device; applying a second polymer layer onto the encapsulant so that the encapsulant is pressed into the opening; and laminating together the first and second encapsulant layers and the encapsulant.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.

Abstract: A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

Abstract: A semiconductor package includes: a die carrier having a first main face and a second main face opposite to the first main face; a semiconductor die disposed on the die carrier, the semiconductor die including a first pad and a second pad; a first electrical connector disposed on the first pad; an encapsulant at least partially covering the semiconductor die, the die carrier, and the first electrical connector; and an insulation layer disposed on the second main face of the die carrier.

Abstract: A chip arrangement is provided. The chip arrangement may include a chip including a first main surface, wherein the first main surface includes an active area, a chip termination portion, and at least one contact pad. A first dielectric layer at least partially covers the chip termination portion and the active area, and at least partially exposes the at least one contact pad, and a second dielectric layer formed by atomic layer deposition over the first dielectric layer and over the at least one contact pad.

Abstract: An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix.

Abstract: A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

Abstract: A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

Abstract: The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the semiconductor wafer. The semiconductor chip separated from such a semiconductor wafer constitutes an electronic component with external contacts in the form of edge contacts. Such an electronic component of semiconductor chip size can be used in diverse ways.