Abstract: The invention relates generally to a sample vial adaptor for interfacing a sample vial with the sample port of a diagnostic instrument, in particular a sample vial containing a patient body fluid sample with the sample port and sample pathway of a multi-use diagnostic instrument. Embodiments of the sample vial adaptor according to the invention generally include a short exterior vent tube having one end in communication with a chamber having a vent, an interior collection tube that is longer than the short exterior vent tube, axially positioned in the lumen of the short exterior vent tube and extending to a capillary outlet that is located on the portion of the inner collection tube that is outside of the short exterior vent tube and outside the vented chamber.

Abstract: The invention relates generally to a sample vial adaptor for interfacing a sample vial with the sample port of a diagnostic instrument, in particular a sample vial containing a patient body fluid sample with the sample port and sample pathway of a multi-use diagnostic instrument. Embodiments of the sample vial adaptor according to the invention generally include a short exterior vent tube having one end in communication with a chamber having a vent, an interior collection tube that is longer than the short exterior vent tube, axially positioned in the lumen of the short exterior vent tube and extending to a capillary outlet that is located on the portion of the inner collection tube that is outside of the short exterior vent tube and outside the vented chamber.

Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

Abstract: An integrated circuit includes programmable logic circuitry and control circuitry that is operable to enable the integrated circuit to make a connection to an external source of data for configuring the programmable logic circuitry. The integrated circuit may include dedicated communications port circuitry that can be used in making the above-mentioned connection, or the programmable logic circuitry itself can be configured for operation as communications port circuitry for use in making the connection. The programmable logic circuitry may be configured any number of times.

Abstract: A light emitting diode (LED) assembly including an LED, an optically transmissive cover and a base for supporting the LED. The optically transmissive cover encapsulates the LED and includes a stiffener for reinforcing a base portion of the cover. The base includes electrical leads extending therefrom that are electrically connected to the LED. To make the cover, at least one support frame is formed in a strip of substantially rigid material. The at least one support frame is connected to a processing portion of the strip. At least one lens is overmolded on the at least one support frame that is connected to the processing portion. The overmolded support frame is removed from the processing portion of the strip.

Abstract: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

Abstract: An LED assembly is manufactured by providing a base on a leadframe, installing an LED within the base, and treating the leadframe with the base thereon to prepare for overmolding. A cover is overmolded onto the leadframe with the base thereon to encapsulate the LED.

Abstract: In a programmable logic device system, including a programmable logic device, a configuration memory device, for storing configuration information, and a host computer system, for generating updated configuration information, the programmable logic device has a JTAG port, for connection to said host computer system, for receiving said updated configuration information, a JTAG port controller, operatively connected to the first JTAG port, and an SPI interface, for connection to said configuration memory device. The JTAG port controller comprises a scan chain, for controlling said SPI interface on the basis of information received from said host computer system. This allows a user of the host computer system to transfer updated configuration data to the configuration memory device by means of a connection from the host computer system to the JTAG port of the programmable logic device.

Abstract: A programmable logic device includes a routing structure, which takes the form of multiple distributed OR gates, which are positioned within the device to allow signals to be input from spaced apart logic elements, and present the input signals to other logic elements, which, again, may be spaced apart throughout the device. Each of the distributed OR gates, and its connections to the other logic elements, acts as a multiplexer. Sufficient of these distributed OR gates are provided to allow a bus structure to be implemented within the device. Since the OR gates are provided separately from the logic elements of the programmable logic device, the required bus structure can be implemented more efficiently.

Abstract: A programmable logic device is provided with multiple power supplies such that, in one mode of operation, power can be disconnected from at least one part of the programmable logic device, while maintaining power at least to an interface component of the programmable logic device, or to a memory component in which current configuration data are stored, thereby avoiding the need for a configuration sequence when power is reapplied to the whole device. The programmable logic device may be provided as an integrated circuit, having multiple pairs of pins for connection to a supply voltage. Each of the pairs of pins provides power for a different subsection of the programmable logic device.

Abstract: A programmable logic device includes a gate array formed from programmable logic elements, and at least one address decoder structure. The address decoder has a first stage, for receiving bits of an address, and for masking out a first group of least significant bits of said address; a second stage, for comparing a second group of most significant bits of said address with respective comparison bits; and a third stage, for providing an output when all of the bits in said second group of bits of said address match their respective comparison bits. Thus, the address decoder can determine when a received address falls within a range of addresses associated with the address decoder. Multiple address decoders may be provided at spaced apart locations within the gate array, and one address decoder can be associated with each slave device implemented in the gate array. The programmable logic device may be used to implement a bus structure, with a bus master which may be in the form of an embedded processor.

Abstract: A light emitting diode (LED) assembly including an LED, an optically transmissive cover and a base for supporting the LED. The optically transmissive cover encapsulates the LED and includes a stiffener for reinforcing a base portion of the cover. The base includes electrical leads extending therefrom that are electrically connected to the LED. To make the cover, at least one support frame is formed in a strip of substantially rigid material. The at least one support frame is connected to a processing portion of the strip. At least one lens is overmolded on the at least one support frame that is connected to the processing portion. The overmolded support frame is removed from the processing portion of the strip.

Abstract: A technique synchronizes logic signals captured in a PLD portion of a PLD system having both a microprocessor and PLD circuitry with executed instructions captured from a microprocessor portion. One or more signal lines connects the microcontroller portion with the PLD portion for transmitting signals between the two portions corresponding to debug operations in each portion. Conventional electronic circuits employing microprocessors and PLD's use independent debugging techniques, either of which are incapable of reflecting the complete state of the circuit at a selected time. Combined processor and PLD systems employ independent clocks for each portion, thus creating additional problems in synchronizing logic state traces in the PLD with the microprocessor instruction traces. The present invention provides a direct signals from the PLD portion to the microcontroller portion upon the occurrence of events relating to debugging and debug modes of the microprocessor.

Abstract: A multiple bus architecture for a system on a chip including bridges for de-coupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

Abstract: A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

Abstract: An integrated circuit includes programmable logic circuitry and control circuitry that is operable to enable the integrated circuit to make a connection to an external source of data for configuring the programmable logic circuitry. The integrated circuit may include dedicated communications port circuitry that can be used in making the above-mentioned connection, or the programmable logic circuitry itself can be configured for operation as communications port circuitry for use in making the connection. The programmable logic circuitry may be configured any number of times.