Patents by Inventor Edward Gamsaragan

Edward Gamsaragan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROCESSOR POWER CONSUMPTION CONTROL AND VOLTAGE DROP VIA MICRO-ARCHITECTURAL BANDWIDTH THROTTLING
    Publication number: 20120210105
    Abstract: A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
    Type: Application
    Filed: August 17, 2011
    Publication date: August 16, 2012
    Inventors: Sanjeev Jahagirdar, Edward Gamsaragan, Scott E. Siers
  • Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
    Patent number: 8028181
    Abstract: A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: September 27, 2011
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Edward Gamsaragan, Scott E. Siers
  • Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
    Publication number: 20100077232
    Abstract: A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 25, 2010
    Inventors: Sanjeev Jahagirdar, Edward Gamsaragan, Scott E. Siers
  • Selective interrupt delivery to multiple processors having independent operating systems
    Patent number: 6976099
    Abstract: A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Varghese George, Edward Gamsaragan, Vladimir M. Pentkovski, Deep K. Buch, Paul Zagacki
  • Selective interrupt delivery to multiple processors having independent operating systems
    Publication number: 20040225790
    Abstract: A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.
    Type: Application
    Filed: June 9, 2004
    Publication date: November 11, 2004
    Inventors: Varghese George, Edward Gamsaragan, Vladimir M. Pentkovski, Deep K. Buch, Paul M. Zagacki
  • Selective interrupt delivery to multiple processors having independent operating systems
    Patent number: 6772241
    Abstract: A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using either a bus-based message or a dedicated interrupt line.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: August 3, 2004
    Assignee: Intel Corporation
    Inventors: Varghese George, Edward Gamsaragan, Vladimir M. Pentkovski, Deep K. Buch, Paul Zagacki
  • Method and apparatus for mapping address space of integrated programmable devices within host system memory
    Patent number: 6748512
    Abstract: A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 8, 2004
    Assignee: Intel Corporation
    Inventors: Deep Buch, Varghese George, Vladimir Pentkovski, Paul Zagacki, Edward Gamsaragan
  • Integrated co-processor configured as a PCI device
    Publication number: 20020073264
    Abstract: An Integrated Co-Processor Configured as a PCI Device is described herein.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Varghese George, Vladimir Pentkovski, Deep Buch, Paul Zagacki, Edward Gamsaragan
  • Method and apparatus for mapping address space of integrated programmable devices within host system memory
    Publication number: 20020073296
    Abstract: A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Deep Buch, Varghese George, Vladimir Pentkovski, Paul Zagacki, Edward Gamsaragan