Patents by Inventor Edward Goggin

Edward Goggin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Virtual machine access to storage via a multi-queue IO storage adapter with optimized cache affinity and PCPU load balancing
    Patent number: 8312175
    Abstract: A method is provided for use in a system that includes a host machine that includes multiple physical CPUs (PCPUs) and at least two cache nodes that are shared by different sets of the PCPUs, comprising: creating in a memory device multiple sets of lanes each lane set associated with a respective PCPU set; tracking levels of processing activity of the PCPUs of each PCPU set; using an MSIX vector value to associate lanes with PCPUs; receiving a IO request from any given PCPU from among the multiple PCPUs; and assigning the IO request to a respective lane based at least in part upon the PCPU set associated with the lane and PCPU processing activity levels.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 13, 2012
    Assignee: VMware, Inc.
    Inventors: Vibhor Patale, Rupesh Bajaj, Edward Goggin, Hariharan Subramanian
  • Virtual Machine Access to Storage Via a Multi-Queue IO Storage Adapter With Optimized Cache Affinity and PCPU Load Balancing
    Publication number: 20110179416
    Abstract: A method is provided for use in a system that includes a host machine that includes multiple physical CPUs (PCPUs) and at least two cache nodes that are shared by different sets of the PCPUs, comprising: creating in a memory device multiple sets of lanes each lane set associated with a respective PCPU set; tracking levels of processing activity of the PCPUs of each PCPU set; using an MSIX vector value to associate lanes with PCPUs; receiving a IO request from any given PCPU from among the multiple PCPUs; and assigning the IO request to a respective lane based at least in part upon the PCPU set associated with the lane and PCPU processing activity levels.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Applicant: VMWARE, INC.
    Inventors: Vibhor Patale, Rupesh Bajaj, Edward Goggin, Hariharan Subramanian