Abstract: A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data in multiple overlapping windows. The CPU is further coupled to one or more input devices which permits a user to selectively position a cursor and input and manipulate data within each of the windows on the display. The windows include defined areas having window features such as text, icons and buttons corresponding to functions to be executed by the CPU. Multiple applications may be executed concurrently by the CPU such that each application is associated with one or more windows. Each display element ("pixel") comprising the display is represented by multiple bits in a computer frame buffer memory coupled to the CPU. An alpha value (.alpha.) is associated with the intensity of each pixel of the display such that multiple images may be blended in accordance with a predefined formula utilizing the alpha values.

Abstract: A touch screen power control function in a computer system, wherein a touch screen input device is employed to control power modes for the computer system. A touch screen controller senses a touch input from the touch screen input device. If the computer system is in a full power mode, the touch screen controller determines the input coordinates corresponding to the touch input, and transfers the input coordinates to a central processing system. If the computer system is in a power down mode, the touch screen controller asserts a main power on signal to a power subsystem, which causes the power subsystem to supply power to the central processing system according to the touch input.

Abstract: A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access memory devices is divided into at least two frame regions. A background image is rendered by a central processing unit into a background frame region within the video memory array. The central processing unit then requests the background image in the background frame region to be copied into a new frame region in the video memory array. A dedicated circuit copies the entire background image in the background frame region into the new frame region. The dedicated circuit operates by using a serial data register within each video random access memory device during the vertical retrace period of a video timing signal. The dedicated circuit performs the background frame copy without requiring any processing resources from the central processing unit.

Abstract: A control device method and apparatus has application for use in multi-media systems. The multi-media system contains a host computer having a video display, a control device and at least one target device. The target device is any remotely controlled equipment that the user wishes to integrate into the multi-media system. The host computer contains a host system configuration which provides the user the ability to select an operating mode for the control device. The control device operates as an interactive user interface to control a cursor on the host computer video display when the control device is placed in the cursor control mode. The user selects a remote control mode to remotely control the target devices using the control device. The host system configuration also includes learn and computer networking modes. In the learn mode, control data information is entered into the host system configuration for new target devices.

Abstract: A central processing unit of a computer system which has an arithmetic logic unit, a register file, an instruction decode/fetch instruction data unit, a bus interface, a multiplexer and a stall cache. The stall cache is coupled to the instruction decode/fetch instruction data unit by a data bus and an internal instruction bus, so that the stall cache can receive and store instructions that have been delayed by an external data fetch during a load or store operation. Upon the next data access, the stall cache allows the delayed instruction to be accessed by the internal instruction bus and to then be processed by the central processing unit without the delay of an external data fetch.

Abstract: A method is provided for writing directly to a frame buffer which provides signals to an output display of a computer system. The computer system has a first processor running a window management program controlling the furnishing of data in a first format to the frame buffer, and a second processor running application programs in a second format for display. A signal is provided from the second processor to the window management program indicating that an application program running on the second processor has information to be displayed. Then a window is set up for the display of the application program running on the second processor under control of the window management program. The second processor is signaled that the window exists and provided information regarding the position and clipping of the window.

Abstract: A paging system which sends and receives encrypted messages. The message may be encrypted either by the sender of the message or by the paging system. Multiple keys may be used for encrypting and decrypting. Public key systems may also be used and integrated into this paging system. The paging system can send out time update messages containing the current time and date. The pagers use the time update messages to automatically update the time in an internal clock. Time stamps can be inserted into the encrypted messages to prevent unauthorized users from replaying old messages.

Abstract: An improved high speed bus and protocol are disclosed that are capable of transferring data in multiple modes. The bus is particularly useful in computer systems that require data transfer between a variety of computer peripheral memory devices. In base transfer mode, the bus is capable of a maximum of 32-bit data transfers while in extended transfer mode, the bus is capable of a maximum of 64-bit data transfers. The bus comprises a plurality of lines including address lines, size lines, data lines and various control lines. In its extended transfer mode, the bus is capable of employing a number of address and control lines as data transfer lines. The bus is also capable of disabling a device when the device is accessed in a transfer mode that the device does not support.

Abstract: Apparatus and methods are disclosed which are most advantageously used with a digital computer for detecting the location of multiple cursors in a computer memory having parity bits. In one embodiment of the present invention, the normal parity checking scheme of the computer memory is modified, such that the parity bit is used to detect data locations containing cursor data. Writing new data to the frame buffer is implemented as a read-modified-write cycle. In another embodiment of the present invention, the parity checking of the computer memory is no longer used as such. Instead, the memory controller has a mode that forces the parity bit to one of two states, independent of the contents of the data location. Rather than writing to the frame buffer as a read-modify-write cycle, the memory controller detects the location of the cursor by reading the state of the parity bit while writing the contents of the data location associated with the parity bit.

Abstract: The interface circuit is intended to be connected between a module terminal and a module itself and provides means for stimulating and sensing signals between the module and its terminal. The interface circuit comprises a decoupling section which connects or disconnects the interface circuit from the module, a test data section for receiving test data from outside sources, an inside section which connects the test data section with the interior of the module and an outside section which connects it with the terminal. A monitor section is also included to allow a terminal to be monitored while it is connected to from its module. The control section requires only four connections and generates the various control signals necessary to control the operation of the interface circuit.