Abstract: A parabolic current generator is provided for use with a waveshaping circuit for producing a sinusoidally increasing bus output voltage signal in response to the rising edge of a data input signal, and a sinusoidally decreasing bus output voltage signal in response to a falling edge of the data input signal. The parabolic current generator provides a current that increases parabolically in response to the rising or falling edge of the data input signal and that decreases parabolically when the bus output voltage signal reaches one-half of its intended full voltage swing or falls below one-half of the full voltage swing to respectively produce the sinusoidally increasing and decreasing voltage at the bus output. The parabolic current generator includes an operational amplifier having an integrating capacitor connected between its non-inverting input and its output. A field effect transistor is connected to its inverting input and has an impedance sized to minimize the capacitor value.

Abstract: A voltage clamping circuit is provided for clamping the input voltage to CMOS devices near the rail voltages so as to prevent forward biased junctions, minority carrier injection and crosstalk between voltage inputs. The voltage clamping circuit receives an input voltage and provides an output voltage within a rail-to-rail voltage range. The clamping circuit has a bias circuit with a PMOS device for providing a p-channel threshold drop to an upper rail voltage so as to generate an upper threshold bias voltage. The bias circuit also has an NMOS device for providing an n-channel threshold increase to a lower rail voltage so as to generate a lower threshold bias voltage. A first clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from rising above the upper rail voltage. A second clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from dropping below the lower rail voltage.

Abstract: An apparatus for providing an EEPROM programming signal, comprises a charge pump circuit for receiving a programming input signal on a programming input line and for charging up a gate drive voltage signal in response to a rising edge of the programming input signal. A transistor that includes a gate coupled to the gate drive signal couples the programming input line to a programming output line, which is coupled to an EEPROM. A ramp control circuit including (i) a capacitor and (ii) a transistor controlling the flow of current through the capacitor, is coupled to the programming output line for regulating a ramp-up rate of a programming output signal on the programming output line. A ramp-down circuit is coupled to the programming input line and to the programming output line and is responsive thereto for providing a ramp-down of the programming output signal after the programming input signal goes low.

Abstract: A circuit apparatus comprises interface circuitry between analog and digital circuitry. A multiple reference circuit provides a variety of reference voltage signals. The multiple reference circuitry is coupled to a selection circuit that selectively couples one of the reference voltage signals to a first reference input of the interface circuitry and selectively couples another of the reference voltage signals to a second reference input of the interface circuitry, whereby the first and second reference inputs may be selectively coupled to the reference voltages and the circuit maintains a ratiometric relationship between the digital and analog circuitry.

Abstract: A MOS hysteresis comparator having a source transistor bias circuit which generates a source current Is that compensates for temperature and manufacturing process variations, thereby providing a hysteresis characteristic which is substantially insensitive to such temperature and manufacturing process variations. The source transistor bias circuit includes a set of MOS transistors which replicate the comparator load currents which occur at the switch points of the comparator, and a source transistor which mirrors the sum of the replicated currents to form the source current Is of the comparator.

Abstract: An apparatus comprises a bandgap reference voltage circuit with first and second current legs and circuitry for generating a bandgap reference voltage. A transistor is coupled to the first current leg for selectively providing current to the first leg of the bandgap reference voltage circuit. A control circuit controls the transistor to turn the transistor on when an external voltage supply is initially applied to the apparatus to provide a start up current to the bandgap voltage reference source and senses an output voltage developed by the bandgap reference current source. The control circuit turns off the transistor responsive to the sensed developed voltage when the sensed developed voltage rises above a predetermined threshold.

Abstract: An integrated circuit apparatus comprises a first stage amplifier and a second stage amplifier. The first stage amplifier is characterized by a cross-coupled integrated layout providing a rail-to-rail swing and a linear gain, A, substantially defined as A=g.sub.m r.sub.o '. The second stage amplifier is coupled to the output of the first stage amplifier and comprises a high-voltage integrated circuit transistor with an AC feedback circuit, the AC feedback circuit comprising, in series, a capacitor, a N+ resistor and an N-WELL resistor, wherein the output of the second stage amplifier is used to directly drive an inductive load.

Abstract: A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide.

Abstract: An electronic circuit configured to pass relatively high voltage signals therethrough when enabled, and block both positive and negative signals when appropriately disabled. The features of the circuit are particularly suited for coupling write and erase voltages to a nonvolatile memory array while integrated on a common chip with the array. In one form, the circuit includes a two-phase pump, which upon being enabled draws a transient current from the high voltage input line and raises the voltage level on an internal capacitive node in closed loop fashion by effecting unidirectional transfers of charge between successive capacitive nodes. The elevated internal voltage provides a driving signal to a driving circuit which passes the high voltage on the input line to an output line without incurring threshold voltage losses.

Abstract: A process for making buried contacts without damaging the surface of the silicon substrate while etching the pattern of a poly interconnect layer. The contact cut made in the gate oxide layer covering the substrate is made smaller than the poly deposited and patterned thereover. Damage to the substrate surface during the etching of the poly layer pattern is prevented by the presence of the gate oxide layer between the poly layer and the substrate. An ion implantation step performed early in the process forms a parasitic depletion mode channel under the region having an overlap of poly onto gate oxide. Consequently, though the gate oxide prevents the direct diffusion of dopant into the underlying substrate when conductors are formed by doping, the parasitic channel ohmically couples the poly interconnect layer to the diffused region in the substrate. The latter region is usually the S/D electrode of an IGFET.