Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: An apparatus for multiplexing a pair of test clock signals and a pair of system clock signals onto a pair of output clock signals includes a first means for coupling a first test clock signal to a first output clock signal when a test mode control signal is active, for driving the first output clock signal to an inactive clock signal level when the test mode control signal transitions to an inactive state, and for coupling a first system clock signal to the first output clock signal beginning with a first full clock pulse of the first system clock signal which occurs after the test mode control signal transitions to the inactive state.

Abstract: A modular two level nine bit shift apparatus has a second level shifter which receives nine input data bits and second level shift signals. The second level shifter shifts the nine data bits by 0, 3 or 6 bit positions according to the second level shift signals and outputs nine second level data bits. A first level shifter receives the nine second level data bits and first level shift signals. The first level shifter shifts the nine second level data bits by 0, 1 or 2, bit positions according to the first level shift signals. The first and second level shifter combine to provide a shift of from 0 to 8 bits. The nine bit shifter can also accommodate eight bit data. The 9 bit shift count is decoded by dividing the count into a first block (0, 1, 2), a second block (3, 4, 5) and a third block (6, 7, 8). Block select signals select one of the first, second and third blocks and the bit select signals select one of the three shift counts within each block.