Abstract: In a processor system with a virtual memory organization and a cache memory table storing the physical addresses corresponding to the most-recenty used virtual addresses, access to the cache table is enhanced by associating upper and lower MSB portions of a virtual address with corresponding upper and lower portions of an associated cache address. The separate cache address portions are placed in separate cache address storage devices. Each cache address storage device is addressed by respective virtual address MSB portions. A physical address storage device stores physical addresses translated from virtual addresses in storage locations addressed by cache addresses associated with the respective virtual addresses from which the physical addresses were translated.