Abstract: A method, system, and computer program product for implementing noise mitigation in dynamic quantum circuits. A condition in a dynamic quantum circuit is identified. A condition refers to a situation or circumstance used to identify or detect a source of noise in the dynamic quantum circuit that may result in an error occurring in the dynamic quantum circuit. For example, the condition may correspond to the idling times, spectator qubits, and idling qubits in cross-talk resistant states (quantum states and in the dynamic quantum circuit. Based on the identified condition, a context-dependent dynamical decoupling sequence is inserted in the dynamic quantum circuit. A context-dependent dynamical decoupling sequence refers to a dynamical decoupling sequence that is inserted in the dynamic quantum circuit based on the context, such as the occurrence of a particular operation (e.g., mid-circuit measurement, the occurrence of a feed-forward operation, the occurrence of qubit shuttling).

Abstract: Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.

Abstract: Techniques regarding compiling quantum circuits with parallelized entangled measurements are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a circuit compilation component that can compile one or more quantum circuits for a hybrid quantum-classical algorithm. The one or more quantum circuits can include a mid-circuit operation to parallelize entangled measurements.

Abstract: Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.

Abstract: A motion compensation module can be used in a video encoder for encoding a video input signal that includes a sequence of images that are segmented into a plurality of macroblocks. The motion compensation module includes a motion search module that generates a motion search motion vector for a plurality of subblocks for a plurality of partitionings of a macroblock of a plurality of macroblocks and generates a selected group of the plurality of partitionings based on a group selection signal. A motion refinement module—generates a refined motion vector for the plurality of subblocks for the selected group of the plurality of partitionings of the macroblock of the plurality of macroblocks, based on the motion search motion vector for each of the plurality of subblocks of the macroblock of the plurality of macroblocks.

Abstract: A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores a plurality of operational instructions including at least one matrix multiply instruction that includes matrix input configuration data. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a matrix multiplier that generates output data based on a multiplication of first input data and second input data in accordance with the matrix input configuration data, wherein the matrix input configuration data indicates the dimensionality of the first input data and the second input data.

Abstract: A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

Abstract: A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The video processing device utilizes an interpolation filter to perform an encoding function in the encoding mode and to perform a decoding function in a decoding mode.

Abstract: A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

Abstract: A motion refinement engine can be used in a video encoder for encoding a video input signal that includes a sequence of images that are segmented into a plurality of macroblocks. The motion refinement engine includes a motion search module, that generates at least one motion search motion vector for a macroblock of the plurality of macroblocks based on a first plurality of directions. A motion refinement module generates at least one refined motion vector for the macroblock of the plurality of macroblocks, based on a second plurality of directions, wherein the second plurality of directions differ from the first plurality of directions. In a further embodiment, motion search, motion refinement, and motion compensation are selectively performed in a single pass.

Abstract: A motion compensation module can be used in a video encoder for encoding a video input signal that includes a sequence of images that are segmented into a plurality of macroblocks. The motion compensation module includes a shared memory and a motion search module that generates a motion search motion vector for a plurality of subblocks for a plurality of partitionings of a macroblock of a plurality of macroblocks and generates a selected group of the plurality of partitionings and stores the selected group of partitionings and the corresponding motion search motion vectors in the shared memory.

Abstract: A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units includes at least one filter vector processor that operates in conjunction with a plurality of programmable filter parameters.

Abstract: A multi-format video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a memory module that stores format configuration data corresponding to a plurality of video coding formats. A plurality of vector processor units generate a decoded video signal from the EDC data, wherein at least one of the plurality of vector processors include a vector function module that generates vector function data based on a vector function of a first input vector and a second input vector. A selection module selects each element of a vector output as one of: a corresponding element of the vector function data, and a corresponding element of a third input vector.

Abstract: A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The encoding mode utilizes a plurality of function specific hardware engines that each perform a specific coding function and the decoding module utilizes at least one of the plurality of hardware engines.

Abstract: A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

Abstract: A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

Abstract: A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

Abstract: A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

Abstract: A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The encoding mode utilizes a plurality of function specific hardware engines that each perform a specific coding function and the decoding module utilizes at least one of the plurality of hardware engines.

Abstract: A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.