Abstract: A furnace with a large quartz tube with a gas inlet on one end, and a large opening at the other end for introducing and withdrawn wafers on a support. At least one small quartz tube is provided within and adjacent the sidewall of the large tube that has a gas inlet on one end outside of the large tube, and apertures in the sidewall. In use, a major stream of gas is provided by a gas inlet on the large tube that flows longitudinally through the large tube. A series of secondary streams of gas are provided from the apertures in the small tube that flow perpendicular to the major stream and across the surfaces of the wafers.

Abstract: An improved apparatus is provided for adjusting a gas injector of a furnace in connection with oxidation, diffusion and heat treating in semiconductor processing. The apparatus includes a reaction tube for serving as a reaction chamber and heat sink. The gas injector is coupled to the reaction tube on one end and includes openings on the other end for passing source gas. An elongated open tube is secured to the gas injector and has its axis superimposed approximately on the axis of the gas injector.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: In a process of fabricating an integrated circuit, a method for uniformly depositing silicon nitride by disposing a plurality of dummy discs beside the production wafers. The dummy discs are made of quartz or silicon carbide. Since the dummy discs can be used longer before been recycled, plenty dummy discs can be saved from disuse. Furthermore, the cost of the management and treatment of the dummy discs is great reduced in this way.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Successive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide.

Abstract: A method of reflowing borophosphosilicate glass wherein wafers on a support that holds the wafers upright in spaced parallel relationship are introduced into a furnace. The wafers are heated to a temperature to achieve reflow while a main stream of heated inert gas is flowed over the wafers in a direction perpendicular to the planes of the substrates, while simultaneously an auxiliary stream of heated inert gas is flowed in a direction perpendicular to the main stream to prevent the formation of BPO.sub.4 crystals during reflow.