Abstract: In one embodiment, a processor includes an execution unit configured to execute one or more threads and a detection unit coupled to detect whether a given thread includes an identifier. The execution unit is further configured to selectively continue execution of the given thread depending upon whether the detection unit detects the identifier.

Abstract: A circuit board including a signal transmission channel includes a dielectric substrate and a signal transmission channel which may be formed on the dielectric substrate. The signal transmission channel may include a conductor, a lossy dielectric material which may longitudinally encapsulate the conductor and a conductive material which may longitudinally encapsulate the lossy dielectric.

Abstract: A test system includes a device under test and a test circuit board. The device under test includes a plurality of contacts configured to provide output signals. The test circuit board may convey the output signals from the device under test to an analyzer. The test circuit board may include a dielectric layer, a via extending through the dielectric layer, a conductor formed on the dielectric layer and a resistive annular ring having a predetermined resistance value. The resistive annular ring may be formed around the via and may be electrically coupled between the via and the conductor.

Abstract: A system and method for correcting data errors. A system for correcting errors in blocks of data received over a communication medium includes an error history unit coupled to an error correction unit. The error history unit may maintain information associated with each bit position of the blocks of data in which a correctable error has occurred. The error correction unit may perform an error correction on a given block of data using an error correction code capable of correcting at least a single bit error and detecting multiple bit errors. Further, in response to detecting a multiple bit error, the error correction unit may correct subsequent errors in the given block of data dependent upon the information maintained by the error history unit.

Abstract: A circuit board including a signal transmission channel includes a dielectric substrate and a signal transmission channel which may be formed on the dielectric substrate. The signal transmission channel may include a conductor, a lossy dielectric material which may longitudinally encapsulate the conductor and a conductive material which may longitudinally encapsulate the lossy dielectric.

Abstract: A test system includes a device under test and a test circuit board. The device under test includes a plurality of contacts configured to provide output signals. The test circuit board may convey the output signals from the device under test to an analyzer. The test circuit board may include a dielectric layer, a via extending through the dielectric layer, a conductor formed on the dielectric layer and a resistive annular ring having a predetermined resistance value. The resistive annular ring may be formed around the via and may be electrically coupled between the via and the conductor.

Abstract: A test system for testing a device under test which includes a plurality of output signal contacts arranged in a particular footprint pattern. The test system may include a test chip which may have a plurality of input signal contacts for receiving signals conveyed from the device under test. The plurality of input signal contacts may be arranged to symmetrically match the particular footprint pattern. The test chip may further include additional contacts for conveying output signals to be analyzed. In addition, the test system includes a test circuit board including a plurality of through-hole vias that connect the plurality of output signal contacts to the plurality of input signal contacts. Further, the test circuit board may include a plurality of blind vias for conveying the output signals to be analyzed to an analyzer unit.

Abstract: A system and method for correcting data errors. A system for correcting errors in blocks of data received over a communication medium includes an error history unit coupled to an error correction unit. The error history unit may maintain information associated with each bit position of the blocks of data in which a correctable error has occurred. The error correction unit may perform an error correction on a given block of data using an error correction code capable of correcting at least a single bit error and detecting multiple bit errors. Further, in response to detecting a multiple bit error, the error correction unit may correct subsequent errors in the given block of data dependent upon the information maintained by the error history unit.

Abstract: A method and system for providing a match on a selected event in performance monitoring of a processing system, the processing system including at least one performance monitor counter (PMC) is disclosed. The method and system comprises initializing the at least one PMC and controlling counting in the at least one PMC based upon the nth occurrence of a match to a specified address, where n is grater than or equal to one.

Abstract: A method and system for monitoring the performance of a processor to detect a set of frequently accessed memory items is provided. A memory region to be monitored is selected and divided into an upper half monitored memory region and a lower half monitored memory region. Memory accesses to the upper half monitored memory region and memory accesses to the lower half monitored memory region are counted during a measurable interval. In response to the count of memory accesses to the upper half monitored memory region being greater than the count of memory accesses to the lower half monitored memory region, the monitored memory region is updated to be equal to the upper half monitored memory region. In response to the count of memory accesses to the lower half monitored memory region being greater than the count of memory accesses to the upper half monitored memory region, the monitored memory region is updated to be equal to the lower half monitored memory region.

Abstract: A method and implementing system are provided in which a service processor is implemented in addition to system processors. The service processor is enabled to access system on-chip registers to acquire system data through the use of the system JTAG bus connections. In one embodiment, logic is provided to determine concurrent calls for use of the same registers by both the system processor(s) and also by the service processor through the JTAG bus. In case of concurrent requests, the JTAG data are held so as not to interfere with system operations until the system processor's use of the registers has been completed.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.

Abstract: The present invention provides a performance monitor including a threshold indicator, a granularity indicator, an event detector, and an event counter. The threshold indicator indicates a number of threshold increments, which each correspond to a number of occurrences of a first event. The granularity indicator indicates the number of occurrences of the first event corresponding to each of the threshold increments indicated by the threshold indicator. The granularity indicator has at least a first state and a second state such that the granularity indicator indicates that a first number of occurrences of the first event correspond to a threshold increment in the first state and that a different second number of occurrences of the first event correspond to a threshold increment in the second state.

Abstract: A processor and method for tracking instruction execution within a processor are described. The processor includes at least one execution unit that executes instructions and an instruction status indicator that dynamically indicates a status of an instruction during processing. The instruction status indicator has at least a first state to which the instruction status indicator is set in order to indicate that execution of the instruction is stalled. In one embodiment, the processor further includes a reason code indicator associated with the instruction status indicator that specifies an event occurrence that caused the indicated instruction status. In another embodiment, the processor further includes a history buffer that indicates the number of processor cycles that the status indicated by the instruction status indicator has remained unchanged.

Abstract: Performance monitoring capabilities are expanded to an entire data processing system so that performance analyses can be made for operations occurring within the entire data processing system and not merely within the processor or any other device containing the performance monitor. Therefore, there is a provision for communicating performance monitor-related signals between the various performance monitors within the various devices and processor within a data processing system.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: A method and system for identifying frequency and length of time of execution of serialization instructions in a pipeline of a processing system, the processing including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least PMCs, includes counting a number of instructions forcing serialization or logically requiring serialization of the pipeline during a predetermined sampling period. Further included are counting a number of additional cycles required to complete the instructions during the predetermined sampling period, and determining a loss of efficiency from the counted number of instructions and the counted number of additional cycles accumulated during the predetermined sampling period.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.