Abstract: Disclosed are multi-function logic circuits which simultaneously receive data signals and control signals. The control signals select logic operations for the multi-function logic circuits to perform on the data signals. Output logic signals, representing the result of the selected logical operation, are generated by the circuits. A four transistor embodiment selectively performs an EXCLUSIVE OR, OR, and NAND operation. A six transistor embodiment selectively performs a FULL ADD, NOR, OR NAND, and AND operation. The six transistor embodiment is suitable for use as an arithmetic logic unit in a digital computer.