Abstract: A high performance peripheral interface device is coupled to a computer via a computer bus and is coupled to a peripheral via a peripheral bus. To speed accessing of consecutively addressed data (the nth datum and the n+1th datum) from the peripheral, the interface device reads the n+1th datum from the peripheral: 1) before the computer has requested the n+1th datum from the interface device, and 2) while the computer is accessing the nth datum from the interface device.

Abstract: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and high performance peripheral interface(s) uses a pipelined architecture to increase use of available data transfer bandwidth. The LBPI coupled between the computer local bus and peripheral interface(s) is provided a pipelined architecture including a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a controlling State Machine with a Configuration Register. The LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation.

Abstract: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s), using a pipelined architecture to increase the use of the available data transfer bandwidth. To accomplish the above, the LBPI, which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or "snooping" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands.

Abstract: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers.

Abstract: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers.

Abstract: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s), using a pipelined architecture to increase the use of the available data transfer bandwidth. To accomplish the above, the LBPI, which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or "snooping" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands.

Abstract: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. The LBPI is coupled between the computer local bus and the peripheral interface(s) and has a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. The LPBI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active.