Patents by Inventor Edward J. Coyne

Edward J. Coyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Junction field effect transistor for voltage protection
    Patent number: 8462477
    Abstract: Apparatus and methods are disclosed, such as those involving a junction field effect transistor for voltage protection. One such apparatus includes a protection circuit including an input, an output, and a JFET. The JFET has a source electrically coupled to the input, and a drain electrically coupled to the output, wherein the JFET has a pinch-off voltage (Vp) of greater than 2 V in magnitude. The apparatus further includes an internal circuit having an input configured to receive a signal from the output of the protection circuit. The protection circuit provides protection over the internal circuit from overvoltage and/or undervoltage conditions while having a reduced size compared to a JFET having a Vp of smaller than 2 V in magnitude.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: June 11, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Eric Modica, Edward J. Coyne, Derek F. Bowers
  • JUNCTION FIELD EFFECT TRANSISTOR FOR VOLTAGE PROTECTION
    Publication number: 20120063049
    Abstract: Apparatus and methods are disclosed, such as those involving a junction field effect transistor for voltage protection. One such apparatus includes a protection circuit including an input, an output, and a JFET. The JFET has a source electrically coupled to the input, and a drain electrically coupled to the output, wherein the JFET has a pinch-off voltage (Vp) of greater than 2 V in magnitude. The apparatus further includes an internal circuit having an input configured to receive a signal from the output of the protection circuit. The protection circuit provides protection over the internal circuit from overvoltage and/or undervoltage conditions while having a reduced size compared to a JFET having a Vp of smaller than 2 V in magnitude.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Eric Modica, Edward J. Coyne, Derek F. Bowers