Abstract: An imaging chip is packaged in transparent injection molded material. The chip may have photosensitive elements arranged in a two-dimensional array on semiconductor material. Each element corresponds to a pixel of an image. The package may be formed of epoxy resin. In one aspect of the invention, the transparent plastic material provides a color filter. Second and third packages with complementary color filters may be used to provide signals for a color imaging system. In another aspect of the invention, a lens is integrated into the plastic package. In another aspect of the invention, a semiconductor chip is applied to a pre-formed plastic package by bump bonding.

Abstract: An imaging chip is packaged in transparent injection molded material. The chip may have photosensitive elements arranged in a two-dimensional array on semiconductor material. Each element corresponds to a pixel of an image. The package may be formed of epoxy resin. In one aspect of the invention, the transparent plastic material provides a color filter. Second and third packages with complementary color filters may be used to provide signals for a color imaging system. In another aspect of the invention, a lens is integrated into the plastic package. In another aspect of the invention, a semiconductor chip is applied to a pre-formed plastic package by bump bonding.

Abstract: Methods for testing semiconductor memory devices are performed during the writing and reading of test information to and from memory cells. During the tests, operational parameters such as commencement of timing signals and the voltage levels thereof which are employed to activate components of a memory device are controllably adjusted in an effort to intentionally imbalance or alter the voltage differential appearing on the bit lines. If the memory device has a defect, the voltage levels on the bit lines are altered to such a degree that the sense amplifier, although properly sensing the voltage differential, incorrectly senses the intended test information stored in the memory cells. As the parameters are manipulated, the test information written from the memory cell and error signals are generated when the information is not the same. Circuitry for performing methods for testing semiconductor memory devices during the writing and reading of test information to and from memory cells is also disclosed.

Abstract: Methods for testing semiconductor memory devices are performed during the writing and reading of test information to and from memory cells. During the tests, operational parameters such as commencement of timing signals and the voltage levels thereof which are employed to activate components of a memory device are controllably adjusted in an effort to intentionally imbalance or alter the voltage differential appearing on the bit lines. If the memory device has a defect, the voltage levels on the bit lines are altered to such a degree that the sense amplifier, although properly sensing the voltage differential, incorrectly senses the intended test information stored in the memory cells. As the parameters are manipulated, the test information written into the memory cells is compared with the test information written from the memory cell and error signals are generated when the information is not the same.

Abstract: A more secure method for selecting and addressing individual integrated circuit chips and memory locations, registers or input/output ports within the chips includes supplying the chips with address information including address checking information, checking the address information actually received in the chip by using an address checking circuit in the integrated circuit, and inhibiting use of the address information in the chip when the address checking circuit indicates an erroneous address. By inhibiting the use of erroneous address information, state information stored in the integrated circuit is not lost. The integrated circuit sends a fault signal requesting retransmission of the address information for recovery from the address fault. Preferably the address checking information is an error detecting and correcting code for correcting single-bit errors and detecting double-bit errors. Then the integrated circuit functions properly with one defective address input.