Abstract: A memory controller for a special purpose digital video processor. To achieve a speed enhancement when using multiple bank memory such as SDRAM, the memory controller arbitrates requests for access to the memory such that, if possible, sequential memory accesses are directed to alternating memory banks. To facilitate access to contiguous blocks of memory such as are often accessed in video signal processing, the memory controller includes an address generator for generating multiple memory addresses in response to a single memory access request. The memory controller further includes features, which permit the use of multiple physical memory configurations. Specifically, the memory controller includes a memory address mapper for translating virtual memory address signals into physical memory address signals for address memory; for different memory configurations, the translation is different.

Abstract: A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8.times.8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16.times.

Abstract: A memory controller for a special purpose digital video processor. To achieve a speed enhancement when using multiple bank memory such as SDRAM, the memory controller arbitrates requests for access to the memory such that, if possible, sequential memory accesses are directed to alternating memory banks. To facilitate access to contiguous blocks of memory such as are often accessed in video signal processing, the memory controller includes an address generator for generating multiple memory addresses in response to a single memory access request. The memory controller further includes features which permit the use of multiple physical memory configurations. Specifically, the memory controller includes a memory address mapper for translating virtual memory address signals into physical memory address signals for addressing memory; for different memory configurations, the translation is different.