Abstract: An apparatus and a method of enhancing data integrity for data transmission over an optical network are disclosed. Upon detecting a low performance condition associated to the optical communications network, an error correcting code (“ECC”) device is activated. The ECC device inserts the ECC to a data stream to form an ECC data stream. Once the ECC data stream reaches to the destination, the ECC device corrects any errors incurred during the transmission, and removes the ECC from the ECC data stream. It should be noted that the ECC device can also be activated by a request from a network operator.

Abstract: Component malfunctions in passive optical networks (PON) can increase bit error rates and decrease signal-to-noise ratio in communications signals. These faults may cause the receivers of the signals, either the optical line terminal (OLT) or optical network terminals (ONTs), to experience intermittent faults and/or may result in misinterpreted commands that disrupt other ONT's communication, resulting in a rogue ONT condition. Existing PON protocol detection methods may not detect these types of malfunctions. An embodiment of the present invention identifies faults in a PON by transmitting a test series of data patterns via an optical communications path from a first network node to a second network node. The test series is compared to an expected series of data patterns. An error rate may be calculated as a function of the differences between the test series and expected series. The error rate may be reported to identify faults in the PON.

Abstract: A soft start circuit for hot installation of modules into an active bus. A very low R.sub.ds MOSFET provides bias through its drain to source path from a bus supply. This path is activated by a gate bias network which charges a capacitor from a supply located on the bus. Further control of the module supply is obtained by circuitry which permits addressing of the module to turn it off or on, temperature sensing to provide thermal protection and current sensing to provide short circuit protection.

Abstract: A method and apparatus for providing communication among N modules connected to a common communication bus uses a bus structure with a reserve line for signaling the occurrence of a reservation time slot during which time each of the N modules which have information to transmit may reserve a time for transmission over the bus. A plurality of at least N data lines are used for transmission of data words over the bus. Each of the N modules are also assigned use of one of the plurality of data lines for signaling during the reservation time slot that the module has information to transmit over the bus. The reserve line is also used for signaling, that a word of data being transmitted over the plurality of data lines is a last word in a current transmission to be transmitted by the module currently transmitting.

Abstract: Disclosed is an arrangement having a main card cage, a plurality of remote card cages, and a data transport system for transmitting synchronous information, the data transport system having at least one bust electrically coupling the card cages to define a plurality of data lines between the main card cage and each of the remote card cages, a master clock generator at the main card cage for generating a single master clock, and a clock resynchronizer at the main card cage for resynchronizing with the master clock data messages received from the remote card cages which have the same frequency, but are shifted in phase from the master clock.

Abstract: An apparatus for controlling access to a time division multiplexed (TDM) bus includes a frame address register having a plurality of storage registers for storing a plurality of frame addresses designated for use in communicating over said TDM bus. A frame address latch stores a current frame address. A frame comparator, coupled to the frame address register and the frame address latch, compares the designated frame addresses with the current frame address and produces a first signal indicative of the storage register containing a frame address matching the current frame address. A time slot register has a plurality of storage registers for storing a time slot number designated for use in communicating over said TDM bus. A time slot generator generates a current time slot number.