Patents by Inventor Edward J. Szczebak, Jr.

Edward J. Szczebak, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140075213
    Abstract: A network connection apparatus and system are described. The network connection apparatus includes a network interface for connection to a communication network, at least one power interface for connection to a powered network device, and at least one communication interface for connection to the powered network device. The communication interface is communicatively coupled to the network interface through a splitter. The network connection apparatus includes a bus connected to the at least one power interface, and a power supply electrically connected to the bus to supply power to the at least one power interface. The network connection apparatus may also include a communication terminal connected to the bus and to the splitter.
    Type: Application
    Filed: January 17, 2013
    Publication date: March 13, 2014
    Applicant: TELLABS BEDFORD
    Inventors: Maoping He, Ning Ou-yang, Richard Schroder, Edward J. Szczebak, JR., Yangong Zhu
  • Publication number: 20090067840
    Abstract: Various service providers have different architectures to deliver Internet Protocol Television (IPTV) to their subscribers. Some service providers equipment is based on layer 2 IPTV protocol, and other equipment is based on layer 3 IPTV protocol. Within a Passive Optical Network (PON) environment, there may be multiple service providers that employ different delivery techniques to Optical Network Terminals (ONTs). Example embodiments of the invention accommodate these different delivery mechanisms by supporting layer 2 and layer 3 delivery by dynamically configuring traffic filters as a function of a layer and content of an upstream traffic request.
    Type: Application
    Filed: September 7, 2007
    Publication date: March 12, 2009
    Inventors: Marc R. Bernard, John A. Stock, Edward J. Szczebak, JR., David P. Fredrickson
  • Patent number: 5652712
    Abstract: A processor controlled test set for testing special service circuits of a telecommunication system. A microprocessor controls the overall operation of the test set, while a digital signal processor provides high speed timing signals to the various test circuits for generating the wave forms used in testing, as well as analyzes the test result signals that are converted into digital signals. A calibration of the test generator signals as well as the signal measuring path is carried out prior to the test sequence. The digital signal processor also provides gain control over a talking path to maintain stability thereof. An I/O circuit of the test set provides plural communication paths between remote equipment and the test set to initiate and carry out various tests. Processors in the I/O module are effective to convert the various protocols of the serial data, by way of software, to digital bit streams usable by the test set.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: July 29, 1997
    Assignee: Reltec Corporation
    Inventors: Edward J. Szczebak, Jr., Chris A. Balthrop, Sr., Patricia K. Mutzabaugh
  • Patent number: 5640433
    Abstract: A processor controlled test set is disclosed for testing special service circuits of a telecommunication system. A microprocessor controls the overall operation of the test set, while a digital signal processor provides high speed timing signals to the various test circuits for generating the wave forms used in testing, as well as analyzes the test result signals that are converted into digital signals. A calibration of the test generator signals as well as the signal measuring path is carried out prior to the test sequence. The digital signal processor also provides gain control over a talking path to maintain stability thereof. An I/O circuit of the test set provides plural communication paths between remote equipment and the test set to initiate and carry out various tests. Processors in the I/O module are effective to convert the various protocols of the serial data, by way of software, to digital bit streams usable by the test set.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: June 17, 1997
    Assignee: Reltec Corporation
    Inventors: Edward J. Szczebak, Jr., Gary D. Stewart
  • Patent number: 5473666
    Abstract: A processor controlled test set is disclosed for testing special service circuits of a telecommunication system. A microprocessor controls the overall operation of the test set, while a digital signal processor provides high speed timing signals to the various test circuits for generating the wave forms used in testing, as well as analyzes the test result signals that are converted into digital signals. A calibration of the test generator signals as well as the signal measuring path is carried out prior to the test sequence. The digital signal processor also provides gain control over a talking path to maintain stability thereof. An I/O circuit of the test set provides plural communication paths between remote equipment and the test set to initiate and carry out various tests. Processors in the I/O module are effective to convert the various protocols of the serial data, by way of software, to digital bit streams usable by the test set.
    Type: Grant
    Filed: September 11, 1992
    Date of Patent: December 5, 1995
    Assignee: Reliance Comm/Tec Corporation
    Inventors: Edward J. Szczebak, Jr., Chris A. Balthrop, Sr., Patricia K. Mutzabaugh, John M. Porter, Gary D. Stewart