Abstract: Buoyant armor for jacketed rounds includes an outer, laminate reinforced strike face having a hardness greater than 640 Brinell. The strike face is configured to strip the jacket off a projectile as it passes through the strike face and to rotate the projectile. An inner, laminate reinforced strike face is separated from the outer, laminate reinforced strike face by a spacer layer. Foam greater than 40 mm thick is disposed behind the inner strike face and is configured to disperse a round and/or its fragments and to provide buoyancy to the armor.

Abstract: Buoyant armor for jacketed rounds includes an outer, laminate reinforced strike face having a hardness greater than 640 Brinell. The strike face is configured to strip the jacket off a projectile as it passes through the strike face and to rotate the projectile. An inner, laminate reinforced strike face is separated from the outer, laminate reinforced strike face by a spacer layer. Foam greater than 40 mm thick is disposed behind the inner strike face and is configured to disperse a round and/or its fragments and to provide buoyancy to the armor.

Abstract: A rotary magnet switch includes a housing defining a cavity for a rotary magnet having a first section rotatable with respect to a second section. A first registration secures the first magnet section to the housing. An actuator extends from a side wall of the housing. The actuator is secured to the second magnet section and is configured to rotate the second magnetic section with respect to the housing and the first magnet section to switch the magnet on and off.

Abstract: Buoyant armor for jacketed rounds includes an outer, laminate reinforced strike face having a hardness greater than 640 Brinell. The strike face is configured to strip the jacket off a projectile as it passes through the strike face and to rotate the projectile. An inner, laminate reinforced strike face is separated from the outer, laminate reinforced strike face by a spacer layer. Foam greater than 40 mm thick is disposed behind the inner strike face and is configured to disperse a round and/or its fragments and to provide buoyancy to the armor.

Abstract: Buoyant armor for jacketed rounds includes an outer, laminate reinforced strike face having a hardness greater than 640 Brinell. The strike face is configured to strip the jacket off a projectile as it passes through the strike face and to rotate the projectile. An inner, laminate reinforced strike face is separated from the outer, laminate reinforced strike face by a spacer layer. Foam greater than 40 mm thick is disposed behind the inner strike face and is configured to disperse a round and/or its fragments and to provide buoyancy to the armor.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.