Patents by Inventor Edward J. Vishnesky
Edward J. Vishnesky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6541349Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.Type: GrantFiled: January 18, 2001Date of Patent: April 1, 2003Assignee: International Business Machines CorporationInventors: Senthilkumar Arthanari, Shaw-Ning Mei, Edward J. Vishnesky
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Patent number: 6531265Abstract: A method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process is described. Shallow recesses on a semiconductor surface are filled with a filling material. The filling material is deposited on the semiconductor surface to a thickness approximately equal to the depth of the shallow recesses. A selectively etchable material is formed on the filling material. A reverse mask (RM) is used to pattern the selectively etchable material to form segments of the selectively etchable material equal to the pattern of the shallow recesses and aligned to the shallow recesses. Exposed filling material is removed followed by the removal of the segments of the selectively etchable material. The remaining filling material in the shallow recesses forms fences which extend above the surface of the semiconductor. The fences are removed resulting in a planar semiconductor surface.Type: GrantFiled: December 14, 2000Date of Patent: March 11, 2003Assignee: International Business Machines CorporationInventors: Shaw-Ning Mei, T. Howard Shillingford, Edward J. Vishnesky
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Publication number: 20020094649Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. The upper regions are covered by a masking layer of nitride having a predetermined thickness. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to a thickness terminating within that of the thickness of the nitride layer. The raised regions of the filler material are then selectively removed in a single planarizing step without removing the filler material in the lowered regions using a fixed abrasive hard polishing pad, as opposed to an abrasive slurry.Type: ApplicationFiled: January 18, 2001Publication date: July 18, 2002Applicant: International Business Machines CorporationInventors: Senthilkumar Arthanari, Shaw-Ning Mei, Edward J. Vishnesky
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Publication number: 20020076653Abstract: A method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process is described. Shallow recesses on a semiconductor surface are filled with a filling material. The filling material is deposited on the semiconductor surface to a thickness approximately equal to the depth of the shallow recesses. A selectively etchable material is formed on the filling material. A reverse mask (RM) is used to pattern the selectively etchable material to form segments of the selectively etchable material equal to the pattern of the shallow recesses and aligned to the shallow recesses. Exposed filling material is removed followed by the removal of the segments of the selectively etchable material. The remaining filling material in the shallow recesses forms fences which extend above the surface of the semiconductor. The fences are removed resulting in a planar semiconductor surface.Type: ApplicationFiled: December 14, 2000Publication date: June 20, 2002Applicant: International Business Machines CorporationInventors: Shaw-Ning Mei, T. Howard Shillingford, Edward J. Vishnesky
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Publication number: 20010036709Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.Type: ApplicationFiled: June 20, 2001Publication date: November 1, 2001Inventors: John W. Andrews, Bao T. Hwang, Howard S. Landis, Shaw-Ning Mei, James M. Tyler, Edward J. Vishnesky
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Patent number: 6270353Abstract: A method is provided for planarizing a structure such as a shallow trench isolation region on a semiconductor substrate. A semiconductor substrate is provided having raised and lowered regions with substantially vertical and horizontal surfaces. The lowered regions may correspond to trench regions. Filler material such as non-conformal high density plasma oxide may be deposited over the horizontal surfaces to at least a thickness equal to a predetermined height so as to provide raised and lowered regions of the filler material. The raised regions of the filler material may then be selectively removed without removing the filler material in the lowered regions.Type: GrantFiled: June 7, 1999Date of Patent: August 7, 2001Assignee: International Business Machines CorporationInventors: John W. Andrews, Bao T. Hwang, Howard S. Landis, Shaw-Ning Mei, James M. Tyler, Edward J. Vishnesky
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Patent number: 6130453Abstract: A flash memory cell comprises a substrate having a trench formed below the substrate surface, a vertical bit line or auxiliary gate deposited in the trench below the surface, a drain region formed in the substrate below the bit line, and a split floating gate deposited in the trench below the surface to a depth less than the vertical bit line. The floating gate includes a first vertical portion on one side of the bit line and a second vertical portion on another side of the bit line opposite the first vertical portion, with each portion of the gate being accessed by the bit line. The memory cell further includes a source region formed below the surface spaced apart from and adjacent each of the floating gate portions and a word line or control gate extending over the substrate, bit line and floating gate portions.Type: GrantFiled: January 4, 1999Date of Patent: October 10, 2000Assignee: International Business Machines CorporationInventors: Shaw-Ning Mei, Edward J. Vishnesky
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Patent number: 5384152Abstract: A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.Type: GrantFiled: June 1, 1993Date of Patent: January 24, 1995Assignee: International Business Machines CorporationInventors: Jack C. Chu, Louis Lu-Chen Hsu, Toshio Mii, Joseph F. Shepard, Scott R. Stiffler, Manu J. Tejwani, Edward J. Vishnesky
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Patent number: 5245206Abstract: A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.Type: GrantFiled: May 12, 1992Date of Patent: September 14, 1993Assignee: International Business Machines CorporationInventors: Jack O. Chu, Louis L. Hsu, Toshio Mii, Joseph F. Shepard, Scott R. Stiffler, Manu J. Tejwani, Edward J. Vishnesky