Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: A collector boost circuit is disclosed for providing a first voltage in a first mode of operation to a power amplifier, and another voltage in a second mode of operation to the power amplifier. The collector boost circuit uses an indicator signal derived by an RF detector to switch between the first and the second mode of operation. The another voltage is a boosted voltage greater than the first voltage and is provided when required during peak excursions to prevent amplifier clipping through a boost capacitor. The another voltage is continuous and varies in accordance with the detected peak signal amplitude.

Abstract: A bias control circuit is provided comprising an input port for receiving a signal indicative of an amplitude of a supply voltage provided to a multi stage power amplifier circuit. Electronic circuitry, electrically coupled to the input port, generates a bias control signal in dependence upon the signal indicative of a supply voltage for provision to a first stage power amplifier of the multi stage power amplifier circuit. The bias control signal is generated such that a gain change of the multi stage power amplifier circuit due to a supply voltage change is substantially compensated.

Abstract: An interface circuit from Common Mode Logic to a low voltage, fixed common mode output, with high current drive. The CML signal is received, and then re-referenced to a low-voltage band-gap supply. The circuit is arranged to provide an output data signal referenced to a second positive reference voltage supply responsive to receipt of a common mode input data signal referenced to a first positive reference voltage supply. The circuit avoids use of vertical PNP transistors in the signal path.

Abstract: An integrated circuit for a telephone instrument provides the basic (POT) service requirement. The transmit and receive channels of the circuit may be fed via controlled attenuators incorporated in a first ancillary circuit to provide hands-free operation. The circuit also includes a current-limited power supply whereby connection to a second ancillary circuit, including an audio amplifier, may be effected to provide loudspeaker operation.