Abstract: Method and program product for analyzing an asynchronously clocked system. The system being analyzed has independently clocked subsystems with clock boundaries therebetween. The model identifies a boundary between the two independently clocked subsystems, and identifies behavior at the boundary between the two independently clocked subsystems. and modeling a latch at the boundary between the two independently clocked subsystems with a behavior model, said behavioral model comprising data receiver time delays.

Abstract: A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format incorporating permutations of the interface specification. The output of the timing diagram editor is a file that describes the interfaces of the logic; this file can contain multiple timing diagrams that describe different interface interactions. A suitable simulation driver reads the file created by the timing diagram editor, learns the interfaces described therein, and uses simulation randomization algorithms to drive the interfaces with legal scenarios for the interfaces described in the timing diagram.