Abstract: Disclosed are systems and methods related to matching an impedance of the power amplifier to an impedance of the antenna in a power amplifier module that includes an amplifier circuit residing on a first semiconductor die and an output matching network (OMN) that includes a first partial OMN and a second partial OMN. The first partial OMN resides on the first semiconductor die and matches an output impedance of the amplifier circuit to an input impedance of the second partial OMN. The second partial OMN matches an output impedance of the first partial OMN with an input impedance of the antenna and is not part of the first semiconductor die.

Abstract: Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a power density translating circuit connectable between the reference device and the amplifier device, the power density matching circuit provided to substantially set a first power density associated with the reference device and a second power density associated with the amplifier device relative to one another, the first power density being a function of the first electrical supply level and the second power density being a function of the second electrical supply level.

Abstract: Circuits and devices related to compensated power detectors. In some embodiments, a power amplifier can include an amplification stage configured to receive a signal at an input and provide an amplified signal at an output, and a detector coupled to the output of the amplification stage and configured to generate a slow-varying or direct-current signal as an input signal representative of power associated with the amplified signal. The detector can be further configured to generate an output signal based on the input signal and a compensation signal resulting from a combination of a first current representative of the input signal and a second current representative of an operating condition associated with the power amplifier.

Abstract: Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.

Abstract: A bias circuit provides additional bias current for power amplifiers during data bursts to compensate for the gain droop caused by a rise in the power amplifier temperature during the data burst. A bias circuit includes a difference amplifier and switches coupled to the difference amplifier. The switches operate the bias circuit in a first mode when a transmit data burst is detected and operate the bias circuit in a second mode after the bias circuit has operated in the first mode for a predetermined period of time. In the first mode, the bias circuit charges a storage capacitor and sets an output current to zero. In the second mode, the bias circuit outputs the output current that increases above the initial value of zero as the PA warms up, where the excursion of this increase of current is determined by a register. The switches disable the bias circuit when the transmit data burst ends.

Abstract: Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.

Abstract: Apparatus and methods for power amplifiers that can operate under a wide range of supply voltages are disclosed herein. In certain implementations, a method of adjusting a parameter of a power amplifier is provided. The method includes detecting a value of a supply voltage provided to the power amplifier. The method further includes selecting a first value from a plurality of values for a first parameter of the power amplifier based on the detected value of the supply voltage. The method further includes adjusting the first parameter of the power amplifier to the first value.

Abstract: Circuits and devices related to compensated power detectors. In some embodiments, a power amplifier can include an amplification stage configured to receive a signal at an input and provide an amplified signal at an output, and a detector coupled to the output of the amplification stage and configured to generate a slow-varying or direct-current signal as an input signal representative of power associated with the amplified signal. The detector can be further configured to generate an output signal based on the input signal and a compensation signal resulting from a combination of a first current representative of the input signal and a second current representative of an operating condition associated with the power amplifier.

Abstract: Methods and apparatus are provided for detection of voltage levels of RF signals. A first voltage correction is provided based on a thermal voltage and a second voltage correction is provided based on a voltage difference between a detection transistor, used for the rectification of the RF signal, and a reference transistor, to which the RF signal is not supplied. Based on the first and second voltage corrections, a more accurate detector with greater linearity may be obtained. In an embodiment, the second voltage correction may be generated proportional to a hyperbolic tangent of the voltage difference between two transistors, obtained using an additional pair of transistors configured as a differential pair. Applications include the control of a power amplifier output in a wireless device.

Abstract: Disclosed are systems and methods related to matching an impedance of the power amplifier to an impedance of the antenna in a power amplifier module that includes an amplifier circuit residing on a first semiconductor die and an output matching network (OMN) that includes a first partial OMN and a second partial OMN. The first partial OMN resides on the first semiconductor die and matches an output impedance of the amplifier circuit to an input impedance of the second partial OMN. The second partial OMN matches an output impedance of the first partial OMN with an input impedance of the antenna and is not part of the first semiconductor die.

Abstract: Disclosed are systems and methods related to reducing intermodulation products in an RF output signal by matching an impedance of the power amplifier to an impedance of the antenna and concurrently blocking signals having a second fundamental frequency received by the antenna when the antenna is transmitting to inhibit intermodulation products of the first and second fundamental frequencies from re-radiating from the antenna. The matching and blocking are performed concurrently by a single circuit with combined matching and blocking functionality.

Abstract: Circuits and methods related to power detectors for radio-frequency (RF) applications. In some embodiments, a power amplifier (PA) system can include a PA circuit having a driver stage and an output stage. The PA system can further include a detector configured to receive a portion of an RF signal from a path between the driver stage and the output stage. The detector can be further configured to generate an output signal representative of power associated with the RF signal and compensated for variation in at least one operating condition associated with the PA circuit.

Abstract: Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a power density translating circuit connectable between the reference device and the amplifier device, the power density matching circuit provided to substantially set a first power density associated with the reference device and a second power density associated with the amplifier device relative to one another, the first power density being a function of the first electrical supply level and the second power density being a function of the second electrical supply level.

Abstract: Circuits and methods related to power detectors for radio-frequency (RF) applications. In some embodiments, a power amplifier (PA) system can include a PA circuit having a driver stage and an output stage. The PA system can further include a detector configured to receive a portion of an RF signal from a path between the driver stage and the output stage. The detector can be further configured to generate an output signal representative of power associated with the RF signal and compensated for variation in at least one operating condition associated with the PA circuit.

Abstract: Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.

Abstract: Power supply noise affects the performance of many amplifier circuits. Power supply noise rejection circuits are typically used in conjunction with amplifier circuits to reduce the effects of the noise. Unfortunately, the main issue with a transimpedance amplifier (TIA) is that it has a single input port and a single output port, and the output ports are often required to be of a differential type in order to interface with a differential input post amplifier circuit. As a result, the conversion from single input port operation to a dual input port configuration for differential operation is often the cause of poor power supply noise rejection. A circuit is thus provided that overcomes the limitations in the prior art by providing a differential TIA for use with a filter circuit and differential amplifier that overcomes the limitations of the prior art.

Abstract: The current flowing in an output field effect transistor is sensed by a parallel circuit arrangement which derives a sensed current representing the current flowing in the output transistor. The parallel circuit arrangement comprises series-connected CMOS transistors which are connected together in order to derive a current output which is representative of the load current through the output transistor. In a short circuit protected output buffer, the sensed current is compared with a reference current and if it exceeds the reference current the amplitude of the drive signal to the output transistor is reduced.

Abstract: A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.