Abstract: A communication device with a synchronized zero-crossing demodulator is described. A synchronizer system (123, 223, 125, 227) and method derives symbol transition timing information from a zero-crossing detector output. The synchronizer (123, 223) is, in one embodiment, connected to the output of a zero-crossing detector (120, 220), to provide an edge clock signal to a phase angle estimator (122, 226), which is passed to a decision device 124, which provides a symbol estimate which is later decoded into an information message. In an alternative embodiment, a synchronizer is combined with the phase angle estimator (125, 227) to provide as an output, a phase angle estimate which is passed to a decision device (124) which provides a symbol estimate signal (127, 229), which is later decoded to obtain the information message.

Abstract: A communication device (100) includes mixers (104) and (108) which mix a local oscillator (112, 106) with a received signal to produce in-phase (i) and quadrature (q) components. The direction of the phase of the signal is detected as it crosses the i and q axes. The direction of the phase rotation is kept track of by a bi-directional counter (123) in order to demodulate multi-level digital signals. A positive rotation increments the bi-directional counter (123). Conversely, a negative direction decrements the counter (123). The final count of the counter (123) is used by a decision device 124 to establish the content of the received information signal.

Abstract: A communication device (100) includes mixers (104) and (108) which mix a local oscillator (112, 106) with a received signal to produce in-phase (i) and quadrature (q) components. The direction of the phase of the signal is detected at the i and q zero crossings. Next, the speed with which the phase rotation angle travels from one zero crossing to another is monitored via a controller (126). The controller (126) manipulates the speed and the direction of the phase rotation angle in order to establish the contents of the received information signal.

Abstract: In an adaptive CDMA receiver (20), a Direct Sequence Spread Spectrum (DS-SS) received signal and a reference signal are equalized by minimizing the error between them. The received signal includes a desired DS-SS communication signal comprising binary bits coded with spreading chip sequences. The received signal is sampled at a chip rate to produce sampled received signals which are correlated with each other. The received samples are partially de-correlated by employing an orthogonal transformation algorithm to provide de-correlated subspace elements and correlated subspace elements. The adaptive equalization process is based on de-correlated and correlated subspace elements. Tap coefficients of a despreading equalizer (400) are updated for the de-correlated and correlated elements individually and collectively, respectively. This selective updating of tap coefficients provides for fast convergence and minimum error.

Abstract: In a CDMA communication system (100) capable of communicating between a receiver (10) and a transmitter (20)direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver chip timing and transmitter chip timing. Transmitter (10) transmits a training bit sequence (31) coded with a spreading chip sequence. The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). The representation of the despreading chip sequence is represented by tap coefficient potentials of the equalizer (400). Receiver chip timing offset is determined based on the tap coefficient potentials.

Abstract: A communication method in an adaptive CDMA communication system (100) capable of communicating a direct sequence spread spectrum communication signals which comprise bit sequences coded with spreading chip sequences. The method includes the steps of transmitting a DS-SS communication signal (30) having a training bit sequence (31) coded with spreading chip sequence. The method includes the step of despreading the DS-SS communication signal based on the training bit sequence (31) during a training interval. The DS-SS communication signals is despread by adaptively determining a despreading chip sequence. Then, following the training interval determining chip timing offset during a chip timing interval. Finally, bit timing offset is determined during a bit timing interval following the chip timing interval.

Abstract: In an adaptive CDMA receiver (20), a DS-SS received signal and a reference signal are equalized by minimizing the error between them the received signal includes a desired DS-SS communication signal comprising binary bits coded with spreading chip sequences. The received signal is sampled at a chip rate to produce sampled received signals which are correlated with each other. The received samples are de-correlated by employing an orthogonal transformation algorithm to provide de-correlated elements corresponding to the received samples. The equalization process is accelerated by minimizing the error based on the de-correlated elements.

Abstract: A code division multiple access (CDMA) communication system (10) for reuse of available spreading codes includes a first communication device (100) and a second communication device (106). The first and second communication devices (100, 106) are capable of identifying spreading codes and operating frequencies that are optimum for their respective radios. The identity of the optimum spreading code and the frequency of the optimum frequency is communicated from one communication device (100) to another (106), hence allowing the two devices to communicate with each other using their respective optimum codes and frequencies. These codes and frequencies may be periodically updated to provide reusability of codes. By dynamically updating codes and frequencies without the use of a central station, the efficiency and reusability of codes in the CDMA system (10) is significantly enhanced.

Abstract: In a CDMA communication system (100) capable of communicating between a receiver (20) and a transmitter (10) direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver bit timing and transmitter timing. Transmitter (10) transmits a training bit sequence (31) followed by a transmitter bit timing sequence (33). The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). Receiver bit timing offset is determined based on the representation of the despreading chip sequence and the transmitter bit timing sequence (33).