Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: A timing controlled converter for converting a time varying input signal to a regulated DC output voltage for application to a load circuit. A feedback loop is employed as a control means for switchably coupling the time varying input signal to the load circuit for controlled periods of time in a manner so as to provide an average load voltage equal to a reference voltage. The duration of the controlled periods of time is a function of: the difference between the time varying input signal and the output voltage; and the integral of the difference between the output voltage and the reference voltage.

Abstract: A high voltage analog switch operable by a binary signal is implemented in a low voltage semiconductor process. The switch has three parallel circuit paths, with each path comprising at least three series connected transistors. Control signals are selectively applied to the control terminals of the transistors to control the switch and selectively turn on or turn off each of the three circuit paths depending on the input voltage range, so that the breakdown voltage of all of the transistors is never exceeded in any mode of operation.

Abstract: A high voltage current source and a voltage expander implemented in a low voltage semiconductor process. The voltage expander extends the operating voltage range of a stack of transistors to multiple times a supply voltage Vdd at the output node of the stack without exceeding the breakdown voltage of any of the transistors in the stack. The voltage expander uses a diode and a voltage divider to detect the output node voltage changes and generates a plurality of voltages that control the gate voltages for the stack of transistors. A high voltage wide swing current source utilizes a transistor to set the output current and the voltage expander to extend the output voltage range of the current setting transistor. An additional transistor and another current source ensure that the output current is constant throughout the entire output voltage range between about 0 V and multiple times the supply voltage Vdd.

Abstract: A high voltage differential pair and op amp implemented in a low voltage semiconductor process. The high voltage differential pair expands the incoming common mode voltage of a differential pair to multiple times the normal operating voltage of the differential pair through the use of high voltage current sources, current sinks and stacks of transistors. The high voltage op amp includes a high voltage input stage and a high voltage common source amplifier to expand the output voltage range to multiple times the normal operating voltage of the op amp.

Abstract: Systems and methods for the pulse edge modulation of digital carrier signals for communications systems which are useful in body implanted electronics. A digital carrier signal is generated and the carrier is pulse edge modulated with digital data. A pulse edge modulated signal is generated by either retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge.

Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.

Abstract: An integrated circuit driver provides, among other things, a high data communication rate, a large common mode output voltage range, avoidance of spikethrough current that increases power consumption, improved switching speed using current-steering techniques, and improved matching of steady-state output current in the high logic state to that of the low logic state. The driver includes complementary differential pairs and associated current mirror circuits that differentially source/sink current at a pair of load conductors to drive the load conductors into a logic state. A single-ended embodiment is also described.

Abstract: An integrated circuit driver provides, among other things, a high data communication rate, a large common mode output voltage range, avoidance of spikethrough current that increases power consumption, improved switching speed using current-steering techniques, and improved matching of steady-state output current in the high logic state to that of the low logic state. The driver includes complementary differential pairs and associated current mirror circuits that differentially source/sink current at a pair of load conductors to drive the load conductors into a logic state. A single-ended embodiment is also described.