Patents by Inventor Edward K. Prem

Edward K. Prem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5098369
    Abstract: A ventricular assist device may include a cardiac compression assembly which comprises a gel-filled pad of generally concave configuration, mounted on a pressure plate with peripheral portions of the pad extending beyond the periphery of the plate, to preclude damage to the heart by the peripheral edges of the plate. The gel-filled pad may have undulating opposite sides formed by intersecting rows of raised dimples. The pad also includes portions for suturing the pad to a heart ventricle, and at least some of the dimples on the side of the pad facing the heart ventricle are provided with ventricle tissue growth-promoting islands. An electrode, in the form of a grid having intersecting strips which define dimple-receiving openings therebetween, also may be mounted on the venticle side of the pad. As many as eight circumferentially arranged cardiac compression assemblies, having lower ends pivotally mounted on a support member adapted to be located adjacent the apex of a heart ventricle, may be provided.
    Type: Grant
    Filed: May 14, 1990
    Date of Patent: March 24, 1992
    Assignee: Vascor, Inc.
    Inventors: Marlin S. Heilman, Steve A. Kolenik, Christopher D. Capone, Carl M. Parisi, Edward K. Prem, Vernon L. Speicher
  • Patent number: 4726024
    Abstract: The fail safe architecture for a computer system includes a read only memory (ROM) self-check module, a random access memory (RAM) self-check module and operation code instructions (op code) self-check module which are actuated periodically by a non-maskable interrupt (NMI) to a microprocessor. The microprocessor then suspends the current applications routine being executed. If the self-check module detects a failure, the microprocessor enters a fail safe trap routine which initially resynchronizes the operation of the microprocessor and then delays the generation of a critical timing pulse (fail safe trigger) with a series of "jump to yourself" steps. The fail safe trigger signal activates a device which sends a fail safe square wave to a narrow bandwidth, digital, band-pass filter.
    Type: Grant
    Filed: March 31, 1986
    Date of Patent: February 16, 1988
    Assignee: Mieczyslaw Mirowski
    Inventors: Robert A. Guziak, Edward K. Prem