Patents by Inventor Edward Kiewra
Edward Kiewra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11774686Abstract: Structures for an edge coupler of a photonics chip and methods of forming an edge coupler for a photonics chip. The structure includes a waveguide core on a dielectric layer, as well as an interconnect structure including a interlayer dielectric layer positioned over the dielectric layer and an opening penetrating through the interlayer dielectric layer to the waveguide core. A region of the interlayer dielectric layer is positioned to overlap with a portion of the waveguide core. The region of the interlayer dielectric layer has a surface that is rounded with a curvature.Type: GrantFiled: May 6, 2021Date of Patent: October 3, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Brett Cucci, Yusheng Bian, Abdelsalam Aboketaf, Edward Kiewra, Robert K. Leidy
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Patent number: 11520113Abstract: Structures for a photodetector or terminator and methods of fabricating a structure for a photodetector or terminator. The structure includes a waveguide core, a light-absorbing layer having a sidewall, and a taper positioned adjacent to the sidewall of the light-absorbing layer. The taper extends laterally from the sidewall of the light-absorbing layer to overlap with the waveguide core, and the taper has a thickness that varies with position relative to the sidewall of the light-absorbing layer. For example, the thickness of the taper may decrease with increasing distance from the sidewall of the light-absorbing layer.Type: GrantFiled: June 24, 2021Date of Patent: December 6, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Abdelsalam Aboketaf, Yusheng Bian, Edward Kiewra, Brett Cucci
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Publication number: 20220357530Abstract: Structures for an edge coupler of a photonics chip and methods of forming an edge coupler for a photonics chip. The structure includes a waveguide core on a dielectric layer, as well as an interconnect structure including a interlayer dielectric layer positioned over the dielectric layer and an opening penetrating through the interlayer dielectric layer to the waveguide core. A region of the interlayer dielectric layer is positioned to overlap with a portion of the waveguide core. The region of the interlayer dielectric layer has a surface that is rounded with a curvature.Type: ApplicationFiled: May 6, 2021Publication date: November 10, 2022Inventors: Brett Cucci, Yusheng Bian, Abdelsalam Aboketaf, Edward Kiewra, Robert K. Leidy
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Publication number: 20220221650Abstract: Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.Type: ApplicationFiled: January 12, 2021Publication date: July 14, 2022Inventors: Yusheng Bian, Roderick A. Augur, Kenneth J. Giewont, Karen Nummy, Edward Kiewra, Steven M. Shank
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Patent number: 11378743Abstract: Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.Type: GrantFiled: January 12, 2021Date of Patent: July 5, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Yusheng Bian, Roderick A. Augur, Kenneth J. Giewont, Karen Nummy, Edward Kiewra, Steven M. Shank
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Patent number: 8895352Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: GrantFiled: June 2, 2009Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Patent number: 8816333Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: GrantFiled: May 29, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Patent number: 8525290Abstract: A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.Type: GrantFiled: June 24, 2011Date of Patent: September 3, 2013Assignees: Macronix International Co., Ltd., International Business Machines CorporationInventors: Erh-Kun Lai, Hsiang-Lan Lung, Edward Kiewra
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Publication number: 20120326265Abstract: A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicants: International Business Machines Corporation, Macronix International Co., Ltd.Inventors: Erh-Kun Lai, Hsiang-Lan Lung, Edward Kiewra
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Publication number: 20120235119Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: ApplicationFiled: May 29, 2012Publication date: September 20, 2012Applicant: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Publication number: 20100301336Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.Type: ApplicationFiled: June 2, 2009Publication date: December 2, 2010Applicant: International Business Machines CorporationInventors: Katherina Babich, Alessandro Callegari, Zhihong Chen, Edward Kiewra, Yanning Sun
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Publication number: 20080001173Abstract: A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.Type: ApplicationFiled: June 22, 2007Publication date: January 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward Kiewra, Steven Koester, Devendra Sadana, Ghavam Shahidi, Yanning Sun
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POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY
Publication number: 20070267386Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.Type: ApplicationFiled: August 3, 2007Publication date: November 22, 2007Inventors: Kaushik Chanda, James Demarest, Ronald Filippi, Roy Iggulden, Edward Kiewra, Ping-Chuan Wang, Yun-Yu Wang -
Publication number: 20070161214Abstract: A method of forming a high k gate stack (dielectric constant of greater than that of silicon dioxide) on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.Type: ApplicationFiled: January 6, 2006Publication date: July 12, 2007Applicant: International Business Machines CorporationInventors: Jean Fompeyrine, Edward Kiewra, Steven Koester, Devendra Sadana, David Webb
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Publication number: 20070158851Abstract: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, James Demarest, Ronald Filippi, Roy Iggulden, Edward Kiewra, Vincent McGahay, Ping-Chuan Wang, Yun-Yu Wang
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Publication number: 20070120259Abstract: A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.Type: ApplicationFiled: January 31, 2007Publication date: May 31, 2007Inventors: Ronald Filippi, Roy Iggulden, Edward Kiewra, Stephen Loh, Ping-Chuan Wang
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POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY
Publication number: 20060254053Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.Type: ApplicationFiled: May 10, 2005Publication date: November 16, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, James Demarest, Ronald Filippi, Roy Iggulden, Edward Kiewra, Ping-Chuan Wang, Yun-Yu Wang -
Publication number: 20060252226Abstract: The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.Type: ApplicationFiled: July 12, 2006Publication date: November 9, 2006Applicant: International Business Machiens CorporationInventors: Zarchary Berndlmaier, Edward Kiewra, Carl Radens, William Tonti
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Publication number: 20060097394Abstract: A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.Type: ApplicationFiled: November 4, 2004Publication date: May 11, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald Filippi, Roy Iggulden, Edward Kiewra, Stephen Loh, Ping-Chuan Wang
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Publication number: 20060073695Abstract: Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.Type: ApplicationFiled: September 30, 2004Publication date: April 6, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ronald Filippi, Roy Iggulden, Edward Kiewra, Ping-Chuan Wang