Abstract: Methods and systems for generating 10-bit control codes for use in 8-bit to 10-bit encoding are disclosed. Such control codes can have low subblock disparity (where subblocks include 6-bit and 4-bit blocks), limited run lengths when concatenated, limited run lengths within sub-blocks, meet minimal allowable cumulative disparity values at predetermined bit locations (not violate a transition matrix), and not form an aliased comma character sequence within a code, or when codes are concatenated with other codes or encoded data values. Preferably, new codes are added to existing 8B10B schemes with less than sixteen control codes to arrive at a control code set of at least sixteen.

Abstract: An apparatus and method for distinguishing a particular gesture from among multiple gestures, performed by a conductive object on the sensing device, using fewer than three time intervals. The apparatus may include a sensing device to detect a presence of a conductive object, and a processing device, coupled to the sensing device, to distinguish the multiple gestures. The method may include distinguishing between a tap gesture, a double tap gesture, a drag gesture, and a motion gesture.

Abstract: A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.

Abstract: A module generally comprising a first transmitter, a detector and a controller. The first transmitter may be configured to transmit through a first physical channel of a connector. The detector may be configured to receive a first status signal but not receive user data through a second physical channel of the connector. The controller may be configured to adjust a power of the first transmitter in response to the first status signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first select signal, a second select signal and a first data stream in response to an input data stream and an exception signal. The second circuit may be configured to generate an output data stream in response to the first data stream, the first select signal and the second select signal. The second circuit may be configured to replace one or more characters of the first data stream.

Abstract: An apparatus comprising a memory, an encoder and one or more registers. The memory may be configured to (i) read and/or write a plurality of state vectors and (ii) read and/or write data. The encoder may be configured to present state vectors to be written in response to (i) data read from the memory (ii) a first address and (iii) a serial data stream. The registers may be configured to present the first address in response to an input address.

Abstract: An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data streams from one or more second serial streams. The second circuit may be configured to transmit the one or more second serial streams in response to the plurality of second source data streams and recover the plurality of first source data streams in response to the one or more first serial streams. The first circuit and the second circuit may be coupled by the one or more pairs of communication channels. The first and second circuits may be configured to transmit simultaneously.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first select signal, a second select signal and a first data stream in response to an input data stream and a redundancy signal. The second circuit may be configured to generate an output data stream in response to the first data stream, the first select signal and the second select signal. The second circuit may be configured to replace one or more characters of the first data stream.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a plurality of control signals and a select signal, in response to (i) a receive clock signal, (ii) a reference clock signal and (iii) a master clock signal. The second circuit may be configured to generate a read signal and a window signal in response to the plurality of control signals. The third circuit may be configured to generate a lock signal in response to (i) the reference clock signal, (ii) the select signal, (iii) the read signal and (iv) the window signal. The receive clock signal and the reference clock signal may be independent clocks configured to provide range control over one or more channels.

Abstract: An apparatus comprising a register circuit, a detector circuit and an output circuit. The register circuit may be configured to present a parallel signal in response to (i) a serial input and (ii) a first clock. The detector circuit may be configured to generate a control signal in response to (i) the parallel signal and (ii) a selection signal. The output circuit may be configured to generate an output in response to (i) the control signal and (ii) the parallel signal.

Abstract: A method and system for serially communicating a stream of data characters having bit-interleaved framing information. One embodiment discloses a method for interleaving a single bit of a frame marker sequence to each data character to demarcate each of the data characters and then serializing the data. The transmitting device serially transmits the data characters with bit-interleaved framing at a high transmission bit rate, over a single communication link. The receiving device captures the data stream and de-serializes the data. It then locates the bit position of the character boundary by detecting a predetermined frame marker sequence located in the same bit position over consecutive data characters. The offset is used to frame the data. A character rate greater than 70 MHz can be realized and a bit transmission rate of greater than 1 Gbit/second can be achieved.

Abstract: A circuit comprising a receiver configured to receive a first signal having a first phase, a second signal having a second phase opposite the first phase and an output configured to present either the first or second signals. A state machine may be configured to receive the output of the receiver circuit and to provide a control signal configured to select the first or second signals.

Abstract: Commands are embedded in data packets of packet characters by inserting at least one command character at an arbitrary place within the data packet among the packet characters. The command characters include at least one distinct differentiation character which is defined to be different from any of the packet characters. The distinct differentiation character allows the command characters to be recognized as command characters rather than packet characters so that the received command may be extracted from the packet characters and the original data packet can be reassembled without the command characters.

Abstract: An interruptible state machine includes a state machine and an interrupt processor. The interrupt processor minimizes the required total number of states for the state machine when it must return to its next "normal" state after an input or interrupt that may occur at any of its normal states. In response to the interrupt, the interrupt processor stores the next state, processes the interrupt, and restores the next state after precessing the interrupt.

Abstract: A circuit and method for framing an input data stream to a periodic signal. The circuit comprises a register circuit, a logic circuit and a multiplexor circuit. The register circuit may be configured to store information and to present a first and second output in response to (i) the input data stream and (ii) the periodic signal. The logic circuit may be configured to (i) detect a predetermined bit sequence and (ii) present a control signal in response to the information stored in the register circuit. The multiplexor circuit may be configured to present one or more multiplexed signals comprising the first and second outputs of the register circuit in response to the control signal.

Abstract: A circuit and method for framing an input data stream to a periodic signal. The circuit comprises a register circuit, a logic circuit and a multiplexor circuit. The register circuit may be configured to store information and to present a first and second output in response to (i) the input data stream and (ii) the periodic signal. The logic circuit may be configured to (i) detect a predetermined bit sequence and (ii) present a control signal in response to the information stored in the register circuit. The multiplexor circuit may be configured to present one or more multiplexed signals comprising the first and second outputs of the register circuit in response to the control signal.

Abstract: A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data packet memories between a data loading mode and a data unloading mode. The controller enables one of the paired data packet memories in the data loading mode and enables the other one of the paired data packet memories in the data unloading mode. The controller switches the modes of the paired data packet memories upon receiving an acknowledgement of moved data.

Abstract: An interruptible state machine includes a state machine and an interrupt processor. The interrupt processor minimizes the required total number of states for the state machine when it must return to its next "normal" state after an input or interrupt that may occur at any of its normal states. In response to the interrupt, the interrupt processor stores the next state, processes the interrupt, and restores the next state after processing the interrupt.

Abstract: In a multiple platter parallel transfer disk drive tolerant of a fault on one channel, data bytes and accompanying parity data are stored to different platters, corresponding with the different channels, of the parallel transfer disk drive. Failure of a channel results in substitution of a predetermined data stream in the channel for the lost data. Data stream substitution is initiated whenever the clock for the channel is not detected within a certain maximum period. Data regeneration is effected from parity data generated for the data prior to storage.

Abstract: A metastable prevent circuit comprises a plurality of parallel channels, each coupled to receive and synchronize asynchronous pulses to a synchronous clock signal. A shift register is responsive to the asynchronous pulses to sequentially enable individual ones of the channels. In the case of a two-channel system, the shift register is a bistable device which enables the channels alternately.