Abstract: Switched capacitor circuit architectures that may enable high efficiency step-up or step-down dc-dc conversion from a primary, fixed supply input voltage using a four-switch switched capacitor topology and a separate auxiliary supply input voltage. The auxiliary supply input voltage can be optimized within the system or chosen from among other readily available supplies in the system to achieve the highest efficiency conversion ratio, without modifying the switch and flying capacitor arrangement. The auxiliary supply input voltage may be applied to other fixed conversion ratio converters to achieve higher efficiency conversion.

Abstract: The present invention provides radio frequency (RF) power controllers that regulate the power output signal of an RF power amplifier using a control signal. The RF power controller includes a power control amplifier that measures the difference between a feedback signal and a power control input signal to supply the control signal to the RF power amplifier. The output power signal is amplitude modulated for a period of time during an enable mode. During the amplitude modulation period, the RF power controller opens the power control loop and maintains a substantially constant output voltage to the RF power amplifier using a second amplifier and a capacitor coupled to power control amplifier. The capacitor is decoupled from the power control amplifier during the amplitude modulation period, and the second amplifier supplies the output voltage of the RF power controller based upon the stored voltage on the capacitor.

Abstract: The invention provides RF power controllers that cancel offset voltages in the power control loop and external offset voltages by coupling the output of the RF power controller to an auto-zero amplifier during STANDBY mode. The auto-zero amplifier controls the output voltage of the RF power controller during each STANDBY mode so as to eliminate the effect of offset voltages. The voltage at the input of the auto-zero amplifier that allows the offset voltages to be canceled is stored during ENABLE mode. The stored voltage is used by the auto-zero amplifier to continue to remove the effect of the offset voltages on the output voltage of the RF power controller during ENABLE mode. Offset drifts due to temperature, power supply changes, etc. are canceled due to frequent offset sampling.

Abstract: A phase locked loop has an average zero phase start circuit to detect and correct for the average phase difference between a data signal and a VCO clock signal over a short interval at the beginning of phase-lock acquisition. The average zero phase start circuit has a data comparator to split the data stream into odd and even portions; odd and even pulse position detectors to detect the phase difference between pulses of the odd and even data signals and corresponding pulses of the VCO clock; and a ramp generator to generate a voltage corresponding to the sum of the detected phase differences. The ramp generator employs a capacitor and switched current sources that discharge the capacitor at a fixed rate to generate the voltage. After 4 phase difference measurements are taken, the VCO is stopped, and another current source discharges the capacitor at 4 times the fixed rate.