Patents by Inventor Edward L. Sill
Edward L. Sill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7255774Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber defining a processing space for containing a substrate to be processed with a plasma formed within the chamber. A dielectric window interfaces with the processing chamber proximate the processing space. A core element formed of a material having a high magnetic permeability is positioned outside of the chamber proximate the dielectric window, and an electrically conductive element surrounds a portion of the core element of high magnetic permeability. The conductive element, when electrical current is conducted thereby, is operable for coupling a magnetic flux into the chamber through the dielectric window for affecting a plasma in the processing space. The core element is configured for directing a portion of the magnetic flux in a direction toward the dielectric window to efficiently couple the channeled flux into the processing chamber through the dielectric window.Type: GrantFiled: September 26, 2002Date of Patent: August 14, 2007Assignee: Tokyo Electron LimitedInventors: Mirko Vukovic, Edward L. Sill
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Publication number: 20040060517Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber defining a processing space for containing a substrate to be processed with a plasma formed within the chamber. A dielectric window interfaces with the processing chamber proximate the processing space. A core element formed of a material having a high magnetic permeability is positioned outside of the chamber proximate the dielectric window, and an electrically conductive element surrounds a portion of the core element of high magnetic permeability. The conductive element, when electrical current is conducted thereby, is operable for coupling a magnetic flux into the chamber through the dielectric window for affecting a plasma in the processing space. The core element is configured for directing a portion of the magnetic flux in a direction toward the dielectric window to efficiently couple the channeled flux into the processing chamber through the dielectric window.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Applicant: Tokyo Electron Limited of TBS Broadcast CenterInventors: Mirko Vukovic, Edward L. Sill
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Patent number: 6596550Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber configured for containing a plasma and a substrate support. Electrodes are coupled to the substrate support and an RF power source is coupled to each of the electrodes for biasing the electrodes to create a DC bias on a substrate positioned on the supporting surface. A first comparator having first and second inputs is electrically coupled to one of the electrodes with an isolating device being coupled between the first and second inputs to isolate the first input from the bias on the one electrode. The comparator has an output reflective of a voltage difference between the first and second inputs. A second comparator has a first input coupled to the first electrode and a second input coupled to the second electrode, and has an output reflective of a voltage difference between the first and second inputs resulting from the bias difference between the first and second electrodes.Type: GrantFiled: March 8, 2002Date of Patent: July 22, 2003Assignee: Tokyo Electron LimitedInventors: Edward L. Sill, William D. Jones, Craig T. Baldwin
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Patent number: 6577113Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber configured for containing a plasma and a substrate support. Electrodes are coupled to the substrate support and an RF power source is coupled to each of the electrodes for biasing the electrodes to create a DC bias on a substrate positioned on the supporting surface. Multiple voltage measurement circuits are electrically coupled to the RF power source and the electrodes to measure voltages at multiple points. A precursor determines the DC bias levels of the electrodes based on the multiple measurement points.Type: GrantFiled: June 6, 2001Date of Patent: June 10, 2003Assignee: Tokyo Electron LimitedInventors: Edward L. Sill, William D. Jones, Craig T. Baldwin
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Publication number: 20020186018Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber configured for containing a plasma and a substrate support. Electrodes are coupled to the substrate support and an RF power source is coupled to each of the electrodes for biasing the electrodes to create a DC bias on a substrate positioned on the supporting surface. Multiple voltage measurement circuits are electrically coupled to the RF power source and the electrodes to measure voltages at multiple points. A precursor determines the DC bias levels of the electrodes based on the multiple measurement points.Type: ApplicationFiled: June 6, 2001Publication date: December 12, 2002Applicant: Tokyo Electron LimitedInventors: Edward L. Sill, William D. Jones, Craig T. Baldwin
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Patent number: 6431112Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber configured for containing a plasma, a substrate support within the chamber, and a plurality of electrodes coupled to the substrate support. The electrodes are each positioned proximate the supporting surface and are electrically isolated from one another. An RF power source is coupled to each of the electrodes for biasing the electrodes, so that they are operable for creating a DC bias on a substrate positioned on the supporting surface. A first electrically capacitive structure is electrically coupled between the RF power source and at least one of the plurality of electrodes. The first electrically capacitive structure has a variable capacitance for varying the DC bias created on the substrate by the at least one electrode relative to the DC bias created on the substrate by at least one of the other electrodes of the plurality of electrodes.Type: GrantFiled: May 4, 2000Date of Patent: August 13, 2002Assignee: Tokyo Electron LimitedInventors: Edward L. Sill, William D. Jones, Craig T. Baldwin
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Publication number: 20020094591Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber configured for containing a plasma and a substrate support. Electrodes are coupled to the substrate support and an RF power source is coupled to each of the electrodes for biasing the electrodes to create a DC bias on a substrate positioned on the supporting surface. A first comparator having first and second inputs is electrically coupled to one of the electrodes with an isolating device being coupled between the first and second inputs to isolate the first input from the bias on the one electrode. The comparator has an output reflective of a voltage difference between the first and second inputs. A second comparator has a first input coupled to the first electrode and a second input coupled to the second electrode, and has an output reflective of a voltage difference between the first and second inputs resulting from the bias difference between the first and second electrodes.Type: ApplicationFiled: March 8, 2002Publication date: July 18, 2002Applicant: Tokyo Electron Limited of TBS Broadcast CenterInventors: Edward L. Sill, William D. Jones, Craig T. Baldwin
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Patent number: 6395095Abstract: A processing system for processing a substrate comprises a process chamber having a top, a bottom, and a sidewall for defining a process space therein. The process chamber has an opening in the sidewall thereof for providing access to the process space. A plasma-generating assembly is coupled with the process chamber for creating a plasma within the process space. A substrate support assembly is configured for coupling with the process chamber to support a substrate within the process space. The substrate support assembly extends into the process space through the sidewall opening in the process chamber and seals the sidewall opening to generally isolate the process space from atmosphere.Type: GrantFiled: June 15, 1999Date of Patent: May 28, 2002Assignee: Tokyo Electron LimitedInventors: William D. Jones, Robert C. Rowan, Edward L. Sill, Thomas J. Licata
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Patent number: 6367413Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber configured for containing a plasma and a substrate support. Electrodes are coupled to the substrate support and an RF power source is coupled to each of the electrodes for biasing the electrodes to create a DC bias on a substrate positioned on the supporting surface. A first comparator having first and second inputs is electrically coupled to one of the electrodes with an isolating device being coupled between the first and second inputs to isolate the first input from the bias on the one electrode. The comparator has an output reflective of a voltage difference between the first and second inputs. A second comparator has a first input coupled to the first electrode and a second input coupled to the second electrode, and has an output reflective of a voltage difference between the first and second inputs resulting from the bias difference between the first and second electrodes.Type: GrantFiled: May 26, 2000Date of Patent: April 9, 2002Assignee: Tokyo Electron LimitedInventors: Edward L. Sill, William D. Jones, Craig T. Baldwin
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Patent number: 6284110Abstract: A passive first-order band reject, or notch, filter characteristic is introduced into a supply and/or return line (18, 20) of a heat transfer system (12) that uses electrically conductive liquid heat transfer medium in contact with radio frequency electrified components (14) typical in sputtering or etching manufacturing equipment. The heat transfer medium line (20) is coiled to create an inherent inductance (L2). A capacitive element (C2) is operatively connected across the coil (29) in the heat transfer medium line (20), the amount of capacitance chosen so that the resonant frequency is at the RF frequency of the components (14) being thermally conditioned. Thus, a high impedance is created for that frequency. The coil (29) and capacitor (C2) combination is protected from physical and electromagnetic interference by an enclosure (44).Type: GrantFiled: April 14, 1999Date of Patent: September 4, 2001Assignee: Tokyo Electron LimitedInventor: Edward L. Sill
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Patent number: 6248251Abstract: A plasma etch apparatus (10) such as that for etching wafers in the manufacture of semiconductors includes a vacuum chamber (15) surrounded by a cylindrical dielectric wall (13). A coil (20) surrounds the chamber outside of the wall and is energized with medium frequency RF energy which is inductively coupled into the chamber to energize a plasma in the chamber to etch a semiconductor wafer (16) on a support (17) in the chamber. A generally cylindrical Faraday shield (30) surrounds the outside of the chamber in contact with the outside of the wall between the wall and the coil. The shield has a plurality of axially oriented slits (32) therein closely spaced around the shield and extending less than the height of the shield. One slit or gap (31) extends the full height of the shield and interrupts an otherwise continuous conductive path around the circumference of the chamber.Type: GrantFiled: February 19, 1999Date of Patent: June 19, 2001Assignee: Tokyo Electron LimitedInventor: Edward L. Sill
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Patent number: 6214720Abstract: A method for improving the efficiency of a plasma process such as a sputter process. A low partial pressure of a gas such as oxygen liberated from a substrate in a reaction chamber is maintained. The low partial pressure may be maintained by providing a plasma gas having a mass that is about equal to or greater than the liberated gas to the reaction chamber at a rate so that the steady state ratio of the plasma gas to the liberated gas is at least 1. The plasma gas is preferably argon. Alternatively a low partial pressure may be maintained by providing an in situ getter or a reactive, condensation or selective pump in the chamber. The method is applicable to a sputter etch or a sputter deposition process.Type: GrantFiled: April 19, 1999Date of Patent: April 10, 2001Assignee: Tokyo Electron LimitedInventors: Edward L. Sill, Thomas Licata
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Patent number: 6130159Abstract: Processing of substrates in a CVD reactor system wherein tungsten silicide is deposited is accomplished with preflow and postflow of reducing gases before and after deposition steps to ensure that tungsten-rich film is not deposited at the interface of the tungsten silicide film to the substrates or on the tungsten silicide film at the end of deposition processing. For systems having a remote gas injection and flow control system connected by a gas supply manifold to a CVD reactor chamber, an isolation valve is provided in the gas supply manifold, and the valve is held closed during at least a portion of time between deposition sequences.Type: GrantFiled: August 3, 1999Date of Patent: October 10, 2000Assignee: Genus, IncInventors: Sien G. Kang, John Y. Adachi, David Badt, Edward L. Sill, Hector Velasco
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Patent number: 5963836Abstract: Processing of substrates in a CVD reactor system wherein tungsten silicide is deposited is accomplished with preflow and postflow of reducing gases before and after deposition steps to ensure that tungsten-rich film is not deposited at the interface of the tungsten silicide film to the substrates or on the tungsten silicide film at the end of deposition processing. For systems having a remote gas injection and flow control system connected by a gas supply manifold to a CVD reactor chamber, an isolation valve is provided in the gas supply manifold, and the valve is held closed during at least a portion of time between deposition sequences.Type: GrantFiled: December 3, 1996Date of Patent: October 5, 1999Assignee: Genus, Inc.Inventors: Sien G. Kang, John Y. Adachi, David Badt, Edward L. Sill, Hector Velasco
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Patent number: 4803173Abstract: An MOS device having a planar configuration in which the top surfaces of the source, drain and gate electrodes are coplanar, and the overlying electrical contact structure is also planar, is produced by a method of fabrication in which the gate is defined by forming an oxide mesa on a substrate, building up the substrate with semiconductor material around the mesa, removing the mesa, and filling the resultant trough with doped polysilicon to form the self-aligned gate. Line width and alignment control are enchanced. The planarity of the device and the improved dimensional control enable a reduction of device dimensions and consequently increased device density in integrated circuits.Type: GrantFiled: June 29, 1987Date of Patent: February 7, 1989Assignee: North American Philips Corporation, Signetics DivisionInventors: Edward L. Sill, Paul G. Hilton