Patents by Inventor Edward L. Smith, Jr.

Edward L. Smith, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085623
    Abstract: According to various embodiments, an array of elements forms an artificially-structured material. The artificially-structured material can also include an array of tuning mechanisms included as part of the array of elements that are configured to change material properties of the artificially-structured material on a per-element basis. The tuning mechanisms can change the material properties of the artificially-structured material by changing operational properties of the elements in the array of elements on a per-element basis based on one or a combination of stimuli detected by sensors included in the array of tuning mechanisms, programmable circuit modules included as part of the array of tuning mechanisms, data stored at individual data stores included as part of the array of tuning mechanisms, and communications transmitted through interconnects included as part of the array of elements.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 14, 2024
    Inventors: Daniel Arnitz, Patrick Bowen, Seyedmohammadreza Faghih Imani, Joseph Hagerty, Roderick A. Hyde, Edward K.Y. Jung, Guy S. Lipworth, Nathan P. Myhrvold, David R. Smith, Clarence T. Tegreene, Yaroslav A. Urzhumov, Lowell L. Wood, JR.
  • Patent number: 5206585
    Abstract: A method for testing an integrated circuit (IC) chip (10) in accordance with the invention comprises the step of forming a solder bump (14) on each of an array of bonding pads (13) on a first surface of the chip, in accordance with the known flip-chip method of IC device packaging. Each of the solder bumps (14) is inserted through an aperture (25) in a spacer member (22), the spacer member having a smaller thickness than the length of each solder bump, whereby each solder bump protrudes through an aperture. The solder bumps are then placed on a layer of anisotropic conductive material (11) which is arranged over an array of test fixture conductive pads so that the anisotropic conductive layer is sandwiched between the IC chip and the test fixture. The integrated circuit chip is then compressed against the anisotropic conductor material to establish electrical contact between the solder bumps of the integrated circuit chip and the test fixture conductor pads (17).
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: April 27, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: David D. C. Chang, Edward L. Smith, Jr.