Abstract: An execution speed controller for controlling the effective processing rate of a microprocessor including an internal cache memory. In one embodiment, the execution speed controller monitors the activities of the microprocessor to determine when it is executing a section of code whose execution should be slowed. When such a determination is made, the execution speed controller periodically asserts at least one control input to the microprocessor. This periodically prevents the microprocessor from accessing the main memory and the internal cache memory, thereby slowing microprocessor execution. In this embodiment, only those software applications requiring slow down are effected. Newer software applications may not require this mode and may run at full speed. An alternate embodiment that does not require a triggering event is also described. In this embodiment, execution of all software applications is slowed down. This is referred to as the "compatibility" mode.

Abstract: A computer system has a dynamically adjustable speed bus. The dynamic speed bus system decreases the length of the bus cycle accesses required for fast peripherals; but, maintains normal (longer) length bus cycles for slower peripherals. Circuitry is provided to decrease the bus cycle length by increasing the clock frequency to the bus controller which controls the bus. When accessing peripherals that can support only normal length bus cycles, the circuitry of the present invention drives the bus controller with the normal lower clock frequency. When accessing faster peripherals, a higher clock frequency is generated such that the waveform transitions smoothly between the low and high bus frequencies. The dynamic speed bus circuitry of the present invention is divided into two logic sections: 1) a decode section and 2) a clock generation section. The decode section identifies faster peripherals that are compatible with shorter bus cycles.

Abstract: An improved method of supporting service requests in certain bus architectures is disclosed. According to the presently invented method, the source, instead of using its own arbitration number, uses the arbitration number of the destination when performing an interrupt or DMA request. The destination then recognizes that it has been granted bus ownership, even though it was not arbitrating for the bus originally. The destination can therefore immediately assume that a request has occurred and immediately thereafter begin its request service routine.