Abstract: A bidirectional GaN FET with a single gate formed by integrating a single-gate bidirectional GaN FET in parallel with a bidirectional device formed of two back-to-back GaN FETs with a common source. The single-gate bidirectional GaN FET occupies most of the integrated circuit die, such that the integrated device has a low channel resistance, while also capturing the advantages of a back-to-back bidirectional GaN FET device.

Abstract: Systems and methods for selectively updating permissions associated with a cloud resource deployment are disclosed. An example method includes receiving a first request to deploy first target cloud resources based on a first specified state defined in a configuration repository, selectively updating deployment permissions associated with the first specified state and deploying the first target cloud resources based at least in part on the first specified state and the updated deployment permissions.

Abstract: The present disclosure generally relates to systems and methods for controlling aerodynamic loads on an aerostructure. The present disclosure can include a system including an outer shell, the outer shell including at least one aperture, and an inner shell having an aperture therethrough. The at least one aperture of the outer shell can be part of an array of apertures azimuthally distributed on the outer shell. The system can further include an actuator configured to control a rotational alignment of one of the inner shell and the outer shell to alter aerodynamic bleed through a portion of the at least one aperture of the outer shell. The actuator can be configured alter the rotational alignment of the inner shell and the outer shell based at least in part on a desired steering direction of the aerostructure.

Abstract: A power supply switch for a gallium nitride integrated circuit. The switch includes two or more parallel n-channel transistor switches (FETs). The FETs are controlled by AC gate waveforms of different phases. The use of multiple AC-controlled FETs allows effective DC operation of a bootstrap inverter circuit without requiring a second DC supply voltage.

Abstract: The present disclosure relates to pharmaceutical suspensions of triamcinolone acetonide, methods of producing such suspensions and methods of using of such suspensions. The pharmaceutical suspensions of the present disclosure are stable and suitable for administration by suprachoroidal injection through a 30-gauge microneedle.

Abstract: Systems and methods for treating a tissue site are described. The system includes an instillation source configured to provide instillation solution to the tissue site, and a negative-pressure source configured to draw fluid from the tissue site to develop a negative pressure at the tissue site. The system also includes a controller communicatively coupled to the instillation source and the negative-pressure source. The controller is configured to actuate the instillation source and actuate the negative-pressure source. The system also includes a sensor communicatively coupled to the controller and operatively coupled to the instillation source and the negative-pressure source. The sensor is configured to generate a signal indicative of an amount of fluid delivered to the tissue site and an amount of fluid recovered from the tissue site.

Abstract: A circuit for synchronizing the turn-on/turn-off times of parallel FETs. The circuit includes a plurality of integrated circuits and a synchronizer. Each of the integrated circuits includes a power FET which operates in parallel with the power FETs of the other integrated circuits, and a phase detector. The phase detector receives and compares the phase output signal of the integrated circuit with the phase output signal of another integrated circuit, and provides signals to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals. The synchronizer, in response to the signals from each of the integrated circuits, reduces or increases the turn-on times of the power FETs, thereby synchronizing the turn-on times of the power FETs.

Abstract: An integrated gate overvoltage protection circuit for protecting the gate of a main field effect transistor (FET). The gate protection circuit includes a blocking FET and a discharge FET connected between the gate and the drain of the main FET. The gate overvoltage protection circuit is configured to turn on both the first FET and the second FET in the event of a fault condition, such that charge from the gate of the main FET is discharged through the first FET and the second FET to the drain of the main FET, thereby protecting the gate of the main FET.

Abstract: A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.

Abstract: The present disclosure relates to pharmaceutical suspensions of triamcinolone acetonide, methods of producing such suspensions and methods of using of such suspensions. The pharmaceutical suspensions of the present disclosure are stable and suitable for administration by suprachoroidal injection through a 30-gauge microneedle.

Abstract: A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can float with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrapping capacitor can be used to charge the synchronous bootstrapping capacitor of another (higher level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply Vdd.

Abstract: Example embodiments of systems and methods for application verification are provided. An application may generate a cryptographic key, and encrypt the cryptographic key with a predefined public key. A server, in data communication with the application, may include a predefined private key. The application may transmit the cryptographic key to the server. The server may receive, from the application, the cryptographic key; decrypt the cryptographic key using the predefined private key; encrypt an authorization token using the decrypted key; and transmit, to the client application, the authorization token via an out-of-band channel. The application may receive, from the server, the authorization token via the out-of-band channel; and decrypt the authorization token to obtain access to one or more services associated with the server.

Abstract: A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.

Abstract: Example embodiments of systems and methods for application verification are provided. An application may generate a cryptographic key, and encrypt the cryptographic key with a predefined public key. A server, in data communication with the application, may include a predefined private key. The application may transmit the cryptographic key to the server. The server may receive, from the application, the cryptographic key; decrypt the cryptographic key using the predefined private key; encrypt an authorization token using the decrypted key; and transmit, to the client application, the authorization token via an out-of-band channel. The application may receive, from the server, the authorization token via the out-of-band channel; and decrypt the authorization token to obtain access to one or more services associated with the server.

Abstract: A bootstrapping circuit that utilizes multiple pre-charged capacitor voltages and applies the capacitor voltages to the high side FET of a GaN bootstrapping driver. During the pre-charging phase of the bootstrapping driver, multiple capacitors are charged in parallel to the supply voltage. During the driving phase of the bootstrapping driver, the capacitors are connected in series through a number of FETs and connected to the gate terminal of the high side FET of the bootstrapping driver. As a result, the gate-to-source voltage of the high side FET is equal to or greater than the supply voltage during the driving phase, increasing the driving capability of the high side FET and reducing the total required capacitance and die area of the bootstrapping driver.

Abstract: A power supply switch for a gallium nitride integrated circuit. The switch includes two or more parallel n-channel transistor switches (FETs). The FETs are controlled by AC gate waveforms of different phases. The use of multiple AC-controlled FETs allows effective DC operation of a supply switch without requiring a second DC supply voltage.

Abstract: A circuit for synchronizing the turn-on/turn-off times of parallel FETs. The circuit includes a plurality of integrated circuits and a synchronizer. Each of the integrated circuits includes a power FET which operates in parallel with the power FETs of the other integrated circuits, and a phase detector. The phase detector receives and compares the phase output signal of the integrated circuit with the phase output signal of another integrated circuit, and provides signals to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals. The synchronizer, in response to the signals from each of the integrated circuits, reduces or increases the turn-on times of the power FETs, thereby synchronizing the turn-on times of the power FETs.