Abstract: Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.

Abstract: Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.

Abstract: A process for implementation on a programmed digital computer includes providing a placement of clusters of cells which are assigned to regions on an integrated circuit chip, and combining the regions to form region groups. The region groups collectively constitute a "jiggle" which resembles a sieve. The clusters in each region group are re-assigned to the regions in the region group. The regions are recombined to form different region groups (a different jiggle), and the clusters in each different region group are re-assigned to the regions in the different region group. These steps are repeated using at least two, preferably four different jiggles, until an end criterion is reached. Then, the regions and clusters are hierarchically subdivided, and the process is repeated for each hierarchical level until the clusters have been reduced to individual cells.

Abstract: A computer implemented method for generating and placing clusters of cells for integrated circuit design includes providing a netlist including cells, and nets of wires interconnecting the cells. A metric is specified for measuring distance between cells as a function of netlist interconnections. A length of a net is the number of cells interconnected by said net minus one, and a distance between two cells is a sum of lengths of nets that provide a shortest path between the cells. A maximum cluster size criterion, such as maximum distance of a cell from the center of a cluster, is specified to provide a desired amount of overlap between clusters. Clusters of cells are generated, each cluster being generated by designating one of the cells as the center, processing the netlist using the metric to determine distances of cells from the center, and assigning cells having progressively increasing distances from the center to the cluster until the maximum cluster size criterion is reached.