Patents by Inventor Edward McGee
Edward McGee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12282662Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.Type: GrantFiled: August 29, 2022Date of Patent: April 22, 2025Assignee: Hewlett Packard Enterprise Development LPInventors: Thomas Edward McGee, Brian J. Johnson, Frank R. Dropps, Derek S. Schumacher, Stuart C. Haden, Michael S. Woodacre
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Publication number: 20250018028Abstract: The technology described herein is directed to compositions and methods for modifying and controlling the activity of cells by expression of proteins from self-amplifying RNA (saRNA). Also described herein are compositions and methods for modifying and controlling the activity of cells by expression of proteins from self-amplifying RNA that is substituted with chemically modified nucleotides.Type: ApplicationFiled: September 6, 2024Publication date: January 16, 2025Applicant: TRUSTEES OF BOSTON UNIVERSITYInventors: Joshua Edward MCGEE, Jack Rainier KIRSCH, Eric BRESSLER, Mark W. GRINSTAFF, Wilson WONG, Lidya Yidnekachew Sertse, Kexin Li
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Publication number: 20240345857Abstract: A first hypervisor running on a first processor cluster is provided. During operation, the first hypervisor can determine a first set of processing nodes and a first memory unit of the first processor cluster in response to the booting up of a first Basic Input/Output System (BIOS) of the first processor cluster. The first hypervisor can discover a second hypervisor running on a second processor cluster comprising a second set of processing nodes and a second memory unit. The first hypervisor can operate, with the second hypervisor, a distributed system comprising the first and second sets of processing nodes and the first and second memory units. The first hypervisor can then operate, with the second hypervisor, a global virtual machine on the distributed system. The virtual memory space of the global virtual machine can be mapped to respective memory spaces of the first and second processor clusters.Type: ApplicationFiled: April 12, 2023Publication date: October 17, 2024Inventors: Brian J. Johnson, Frank R. Dropps, Derek S. Schumacher, Thomas Edward McGee
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Patent number: 12115217Abstract: The technology described herein is directed to compositions and methods for modifying and controlling the activity of cells by expression of proteins from self-amplifying RNA (saRNA). Also described herein are compositions and methods for modifying and controlling the activity of cells by expression of proteins from self-amplifying RNA that is substituted with chemically modified nucleotides.Type: GrantFiled: November 17, 2023Date of Patent: October 15, 2024Inventors: Joshua Edward McGee, Jack Rainier Kirsch, Eric Bressler, Mark W. Grinstaff, Wilson Wong, Lidya Yidnekachew Sertse, Kexin Li
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Publication number: 20240197860Abstract: The technology described herein is directed to compositions and methods for modifying and controlling the activity of cells by expression of proteins from self-amplifying RNA (saRNA). Also described herein are compositions and methods for modifying and controlling the activity of cells by expression of proteins from self-amplifying RNA that is substituted with chemically modified nucleotides.Type: ApplicationFiled: November 17, 2023Publication date: June 20, 2024Applicant: Trustees of Boston UniversityInventors: Joshua Edward MCGEE, Jack Rainier KIRSCH, Eric BRESSLER, Mark W. GRINSTAFF, Wilson WONG, Lidya Yidnekachew Sertse, Kexin Li
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Publication number: 20240069742Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Inventors: Thomas Edward McGee, Brian J. Johnson, Frank R. Dropps, Derek S. Schumacher, Stuart C. Haden, Michael S. Woodacre
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Publication number: 20230325867Abstract: A method implemented on an electronic computing device includes receiving a request for an automated teller machine (ATM) transaction from an ATM. Authentication credentials are received of a customer of the ATM. The authentication credentials are associated with the request for the ATM transaction. A notification is received of a failure to execute the ATM transaction at the ATM. In response to the receiving a notification of the failure, a fee modification is issued to the customer of the ATM. The fee modification permits modification of a transaction fee associated with a subsequent ATM transaction at an alternative ATM.Type: ApplicationFiled: May 30, 2023Publication date: October 12, 2023Inventors: Joseph De Frank, Darren M. Goetz, Michael Edwards McGee, Dennis E. Montenegro
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Patent number: 11704687Abstract: A method implemented on an electronic computing device includes receiving a request for an automated teller machine (ATM) transaction from an ATM. Authentication credentials are received of a customer of the ATM. The authentication credentials are associated with the request for the ATM transaction. A notification is received of a failure to execute the ATM transaction at the ATM. In response to the receiving a notification of the failure, a fee modification is issued to the customer of the ATM. The fee modification permits modification of a transaction fee associated with a subsequent ATM transaction at an alternative ATM.Type: GrantFiled: January 13, 2020Date of Patent: July 18, 2023Assignee: Wellls Fargo Bank, N.A.Inventors: Joseph De Frank, Darren M. Goetz, Michael Edwards McGee, Dennis E. Montenegro
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Patent number: 11188480Abstract: Systems and methods are provided for addressing die are inefficiencies associated with the use of redundant ternary content-addressable memory (TCAM) for facilitating error detection and correction. Only a portion of redundant TCAMs (or portions of the same TCAM) are reserved for modified coherency directory cache entries, while remaining portions are available for unmodified coherency directory cache entries. The amount of space reserved for redundant, modified coherency directory cache entries can be programmable and adaptable.Type: GrantFiled: May 12, 2020Date of Patent: November 30, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Frank R. Dropps, Thomas Edward McGee
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Publication number: 20210357334Abstract: Systems and methods are provided for addressing die are inefficiencies associated with the use of redundant ternary content-addressable memory (TCAM) for facilitating error detection and correction. Only a portion of redundant TCAMs (or portions of the same TCAM) are reserved for modified coherency directory cache entries, while remaining portions are available for unmodified coherency directory cache entries. The amount of space reserved for redundant, modified coherency directory cache entries can be programmable and adaptable.Type: ApplicationFiled: May 12, 2020Publication date: November 18, 2021Inventors: FRANK R. DROPPS, THOMAS EDWARD MCGEE
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Patent number: 9654142Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: GrantFiled: July 18, 2014Date of Patent: May 16, 2017Assignee: SILICON GRAPHICS INTERNATIONAL CORP.Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Patent number: 9122816Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.Type: GrantFiled: November 14, 2014Date of Patent: September 1, 2015Assignee: Silicon Graphics International Corp.Inventor: Thomas Edward McGee
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Publication number: 20150074375Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventor: Thomas Edward McGee
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Patent number: 8892805Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.Type: GrantFiled: March 7, 2013Date of Patent: November 18, 2014Assignee: Silicon Graphics International Corp.Inventor: Thomas Edward McGee
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Publication number: 20140337691Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: ApplicationFiled: July 18, 2014Publication date: November 13, 2014Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Publication number: 20140258679Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Silicon Graphics International Corp.Inventor: Thomas Edward McGee
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Patent number: 8812721Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: GrantFiled: December 4, 2012Date of Patent: August 19, 2014Assignee: Silicon Graphics International Corp.Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Publication number: 20130198301Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: ApplicationFiled: December 4, 2012Publication date: August 1, 2013Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Patent number: 8327015Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: GrantFiled: January 18, 2011Date of Patent: December 4, 2012Assignee: Silicon Graphics International Corp.Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Patent number: D648398Type: GrantFiled: April 12, 2010Date of Patent: November 8, 2011Assignee: The Procter & Gamble CompanyInventor: Brian Edward McGee