Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled between the at least one host channel of the memory sub-system controller and to the memory device to connect the plurality of memory die to the memory sub-system controller. The at least one I/O expander circuit is to limit an impedance load presented on the at least one host channel to an impedance load of a corresponding subset of the plurality of memory die selected during a given time period.

Abstract: A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.

Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled between the at least one host channel of the memory sub-system controller and to the memory device to connect the plurality of memory die to the memory sub-system controller. The at least one I/O expander circuit is to limit an impedance load presented on the at least one host channel to an impedance load of a corresponding subset of the plurality of memory die selected during a given time period.

Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled to the at least one host channel of the memory sub-system controller and to the memory device. The at least one I/O expander circuit includes one or more I/O buffers to send and receive signals on the at least one host channel, a selection circuit coupled to the one or more I/O buffers, and command processing logic to enable the selection circuit to route the signals on a selected one of a plurality of expansion channels coupled to the at least one I/O expander circuit. Each of the plurality of expansion channels is coupled to a corresponding subset of the plurality of memory die.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled to the at least one host channel of the memory sub-system controller and to the memory device. The at least one I/O expander circuit includes one or more I/O buffers to send and receive signals on the at least one host channel, a selection circuit coupled to the one or more I/O buffers, and command processing logic to enable the selection circuit to route the signals on a selected one of a plurality of expansion channels coupled to the at least one I/O expander circuit. Each of the plurality of expansion channels is coupled to a corresponding subset of the plurality of memory die.

Abstract: Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

Abstract: A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.

Abstract: An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.

Abstract: Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

Abstract: Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

Abstract: An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

Abstract: Method and system for assigning port addresses for a plurality of network devices based on a link rate associated with each network device is provided. The method includes discovering a link rate associated with each of the plurality of network devices; assigning a device address for each of the plurality of network devices, where at least a portion of the device address is selected based on the discovered link rate; assigning communication lanes among the plurality of network devices for network communication, wherein the communication lanes are assigned such that network devices with similar link rates use a same communication lane.

Abstract: Method and system for processing frames in a fibre channel network is provided. The method includes, determining if an incoming frame in a port of a fibre channel switch includes a FR_Header with a time to live time (“TTLT”) field value; determining if the TTLT field value is greater than a certain number; adjusting the TTLT field value at a pre-determined time interval if the TTLT field value is greater than the certain number; and inserting an adjusted TTLT field value in the incoming frame before it is sent out. The switch element includes, a port that receives an incoming frame and determines if a FR_Header with a time to live time (“TTLT”) field value is received with the FR_Header, and using a timer adjusts the TTLT field value and inserts the adjusted TTLT field value in the incoming frame, before it is sent out.