Abstract: A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage.The bias circuit comprises an amplifier and a p-type FET, where the drain of the p-type FET is fed back to a non-inverting input of the amplifier, and a reference voltage is applied to an inverting input of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor is connected to the drain of the p-type FET, to determine the current at the drain of the p-type FET. The weighted current source is made up of FETs having similar operating characteristics as the p-type FET of the bias circuit.

Abstract: A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons the determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.Control circuitry is also provided to allow for successive conversions using only a single address read.

Abstract: A system for use in a bar code processing system using a combination of a first derivative signal and a second derivative signal to determine the bar edge. The predominant signal in determining the edge is the second derivative signal. A zero-cross of the second derivative signal occurs at the bar edge. The first derivative signal is used to qualify the point in time in the second derivative signal for which a zero-cross is examined the system is particularly suited for near filled operation.

Abstract: A resolution enhancer circuit provides an increased resolution capability for an A/D converter. The resolution enhancer circuit receives as input an analog input signal having a range greater than the effective range of the A/D, and prescales the input signal to a range that is within the common mode range of op amps used within the resolution enhancer circuit. The input signal can also have a range much less than the effective range of the A/D, and then it would be increased by the prescaler to be within an operable range of the A/D. The prescaled signal is provided to a sampling circuit, which samples the prescaled signal at times determined to be near-saturation conditions of the A/D. A magnified difference between the prescaled signal and the sampled signal, biased to the sampled signal, is then input to the A/D, which determines a number of A/D counts based on that value.

Abstract: A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage. The bias circuit comprises an amplifier and a p-type FET, where the drain of the p-type FET is fed back to a non-inverting input of the amplifier, and a reference voltage is applied to an inverting input of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor is connected to the drain of the p-type FET, to determine the current at the drain of the p-type FET. The weighted current source is made up of FETs having similar operating characteristics as the p-type FET of the bias circuit.

Abstract: A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.Control circuitry is also provided to allow for successive conversions using only a single address read. A one-half clock cycle reset occurs at the start of every MSB comparison for every n-bit read, and this reset goes to every component in the A/D except the latch for the LSB, which must be held for at least one more clock cycle before since it has not yet been output to the data bus as yet.

Abstract: A video brightness control system for high performance CRT displays including a buffer amplifier for receiving high speed video information and applying it to a gain control variable resistor serving as a contrast control. An ambient light sensor drives a nonlinear amplifier to provide an ambient light signal which is in proportion to the logarithm of the ambient light level over a wide range. A manual brightness control potentiometer is adjustable to provide a constant brightness signal. The video information signal, the ambient light signal, and the manual brightness control signal are added together by a summing device, with the resultant signal approximating a logarithmic characteristic. The output of the summing device is applied to a gamma correction amplifier which drives a video driver amplifier, the video amplifier, in turn, drives the CRT.