Abstract: A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time periods when data is being repeated, thus increasing display memory bandwidth. Display data from a location in display memory is stored in a latch, and is output from the latch until the tag information indicates no more data repetitions occur.

Abstract: An asynchronous video system provides for the appropriate pixel data to be displayed. The system maps display control signals into a memory clock while maintaining the appropriate relationship with pixel data. Therefore, the display control signals are generated using the memory clock. Hence, no synchronization circuit is necessary to ensure that the memory control circuit and display control circuit are running at the same frequency.

Abstract: The present invention provides a fast bit blitter method and circuit which uses less logic than do prior art bit blitter circuits. A circuit built in accordance with the present invention includes four main components each of which only has as many bit positions as does the data bytes that are being shifted. The four main components are a storage register, a multiplexer bank, a multiplexer selector and a barrel shifter. As data words are serially read out of memory, they are temporarily stored in the register. The multiplexer gates selected bit from the word stored in the register, together with selected bits from the next word that appears on the data bus to the barrel shifter. The barrel shifter does the appropriate shifting. Alternatively, the barrel shifter can be located before the multiplexer in the data path.