Abstract: A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.

Abstract: The present invention includes a system that has been developed to vary the starting and stopping of a pulse train of arbitrary phase without glitches, spurious pulses, or spurious change in duty cycle. This is accomplished by a system for generating a gated periodic waveform, the system includes a generator for generating a periodic waveform of adjustable phase; a device for providing a delayed enable signal based on the phase of the periodic waveform so that the gated periodic waveform can be started and stopped without creating undesirable changes in the gated periodic waveform; and a logic element for generating a gated periodic waveform based on the delayed enable signal and the periodic waveform of adjustable phase.

Abstract: The present invention includes a system that has been developed to vary the starting and stopping of a pulse train of arbitrary phase without glitches, spurious pulses, or spurious change in duty cycle. This is accomplished by a system for generating a gated periodic waveform, the system includes a generator for generating a periodic waveform of adjustable phase; a device for providing a delayed enable signal based on the phase of the periodic waveform so that the gated periodic waveform can be started and stopped without creating undesirable changes in the gated periodic waveform; and a logic element for generating a gated periodic waveform based on the delayed enable signal and the periodic waveform of adjustable phase.

Abstract: A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.

Abstract: A clock generator for providing programmable control of an output clock, the clock generator includes a mechanism for creating a plurality of clocks offset in phase; two programmable selectors for selecting two clocks from the plurality of clocks; and logic for combining the two selected clocks to create an output clock with any combination of offset, if any, and width.

Abstract: A timing generator for controlling an image sensor, the timing generator includes a first output driver that is continuously supplying a current to an output; a second output driver that is connected in parallel with the first output driver and that is selectively energized for supplying an additional current to the output; a controller that is electrically connected to the second driver which, based on the resulting waveform at the output, is adjusted to either supply its current or not supply its current for varying a total current to the output to control an image sensor.

Abstract: A digital data system includes a circuit for controlling data transfer between a four byte wide pathway, such as a VME bus, and a byte wide device, such as a SCSI disk drive by way of a byte wide bus (SCSI bus). The control circuit effects selective data transfer of an odd or even data byte, a data short word (two parallel bytes) or a data long word (four parallel bytes). The transfer circuit includes a four byte wide data register connected to the VME bus, four, byte wide, funnel registers connected in parallel to the data register, a byte wide FIFO memory connected between the funnel registers and the SCSI disk drive via a SCSI bus. A DMA controller and funnel controller state machine control transfer of data from the VME bus to the SCSI disk drive either as a data byte, a data short word or a data long word.

Abstract: A digital data system includes a circuit for controlling data transfer between a byte wide device, such as a SCSI disk drive, to a four byte wide pathway such as VME bus. The control circuit effects selective control of data transfer of an odd byte, an even byte, a short word (two parallel bytes), or a long word (four parallel bytes). The control circuit includes a FIFO memory, prefetch registers, MUXs, a VME data register, a state machine and DMA controller.

Abstract: Apparatus for processing a digital image from a medical diagnostic imaging device. The apparatus includes an image memory, a configurable window width/level or combined window width/level and curve shape look-up table in the input data path to the memory and a curve shape look-up table in the output data path from the memory. The look-up tables and the image memory can handle digital images of different bit length through software control. This increases image processing versatility, minimizes image memory size, and reduces image transfer time.