Abstract: Fabrication methods and structure include: providing a wafer with at least one fin extended above a substrate in a first region, and at least one fin extended above the substrate in a second region of the wafer; forming a gate structure extending at least partially over the at least one fin to define a semiconductor device region in the first region; implanting a dopant into the at least one fin in the first region and into the at least one fin in the second region of the wafer, where the implanting of the dopant into the at least one fin of the second region modulates a physical property of the at least one fin to define a resistor device region in the second region; and disposing a conductive material at least partially over the at least one fin in the first region and over the at least one fin in the second region of the wafer, in part, to form a source and drain contact in the first region, and a fin-type metal-semiconductor resistor in the second region.

Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

Abstract: The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.

Abstract: The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.

Abstract: The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.

Abstract: A method for forming a semiconductor device includes forming gate stacks on a crystalline semiconductor layer; depositing a spacer layer over a top and sidewalls of the gate stacks; recessing the semiconductor layer between the gates stacks; and depositing a non-conformal layer over the gates stacks and within the recesses such that the non-conformal layer forms a pinch point over the recesses. The non-conformal layer is etched at a bottom of the recesses through the pinch point to expose the semiconductor layer. Dopant species are implanted at the bottom of the recesses through the pinch point in the semiconductor layer. The non-conformal layer is stripped, and source and drain material is grown in the recesses. The dopant species are activated to form PN junctions to act as a junction butt between portions of the semiconductor layer.

Abstract: Embodiments of the present invention provide a finFET and method of fabrication to achieve advantages of both merged and unmerged fins. A first step of epitaxy is performed with either partial diamond or full diamond growth. This is followed by a second step of deposition of a semiconductor cap region on the finFET source/drain area using a directional deposition process, followed by an anneal to perform Solid Phase Epitaxy or poly recrystalization. As a result, the fins remain unmerged, but the epitaxial volume is increased to provide reduced contact resistance. Embodiments of the present invention allow a narrower fin pitch, which enables increased circuit density on an integrated circuit.

Abstract: The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.

Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

Abstract: A method for forming a semiconductor device includes forming gate stacks on a crystalline semiconductor layer; depositing a spacer layer over a top and sidewalls of the gate stacks; recessing the semiconductor layer between the gates stacks; and depositing a non-conformal layer over the gates stacks and within the recesses such that the non-conformal layer forms a pinch point over the recesses. The non-conformal layer is etched at a bottom of the recesses through the pinch point to expose the semiconductor layer. Dopant species are implanted at the bottom of the recesses through the pinch point in the semiconductor layer. The non-conformal layer is stripped, and source and drain material is grown in the recesses. The dopant species are activated to form PN junctions to act as a junction butt between portions of the semiconductor layer.

Abstract: An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.

Abstract: An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.

Abstract: An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.

Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.

Abstract: Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.