Abstract: A master-slave multiprocessor (FIG. 1) is formed by connecting a slave processor (25) to an I/O slot of a uniprocessor, and by minimally modifying the uniprocessor's operating system. At initialization, one routine (FIG. 5) redirects slave interrupt vectors (200) to point to a common interrupt handler (FIG. 12). Before a process executes on the slave processor, another routine (FIGS. 9 and 10) corrupts execution stack bounds (217, 218) of the process. A non-interrupt operating system call during execution of the process causes an automatic firmware check (FIG. 3) of the execution stack pointer (203) against the stack bounds. Occurrence of an interrupt or encounter of a stack exception results in suspension of process execution and invocation of the interrupt handler or a slave stack exception handler (FIG. 11), respectively. Each handler calls a slave delete routine (FIG. 15) to restore the process' stack bounds to valid values and to transfer the process for execution to the master processor (12).

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus.

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus.

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space; a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus.