Abstract: A method of integrating an optoelectronic device comprising a Pockels material, such as lithium niobate (LiNbO3), includes forming an optoelectronic device layer over a semiconductor layer. The optoelectronic device layer includes a patterned optoelectronic device segment in an interlayer dielectric. A window is etched in the interlayer dielectric using the patterned optoelectronic device segment as a sacrificial etch stop. The patterned optoelectronic device segment is removed in the window. The optoelectronic device comprising the Pockels material is formed in place of the removed patterned optoelectronic device segment. The optoelectronic device comprising the Pockels material may be formed from an optoelectronic chiplet.

Abstract: A method of forming a semiconductor structure having a first substrate capable of electrically and mechanically connecting to a second substrate includes providing a first substrate without a solder bump. A solder bump receiving metal is formed over a top interconnect metal of the first substrate. The solder bump receiving metal may include platinum, a platinum alloy, nickel, or a nickel alloy. A passivation layer is formed, wherein the passivation layer is not situated under any portion of the solder bump receiving metal. A window is formed exposing a portion of the solder bump receiving metal. The method may further include providing a second substrate with a second substrate solder bump. The second substrate solder bump may be mechanically and electrically connecting to the exposed portion of the solder bump receiving metal of the first substrate.

Abstract: One exemplary method of forming a semiconductor structure having a platinum-based solder body contact includes providing a semiconductor structure having a passivation layer over a surface thereof, the passivation layer having a window exposing a portion of a top metal pad, and forming a barrier metal stack over the passivation layer and the portion of the top metal pad, the barrier metal stack including a tantalum nitride (TaN) layer and a tantalum (Ta) layer. The method further includes forming a solder body contact layer comprising platinum (Pt) over the barrier metal stack, and patterning the solder body contact layer and the barrier metal stack to form the platinum-based solder body contact over the portion of the top metal pad.

Abstract: A semiconductor structure has a substrate and a thermally-tunable photonics device in or over the substrate. A tantalum nitride (TaN) resistive heater is over the substrate and proximate to the thermally-tunable photonics device. The TaN resistive heater is configured to tune the thermally-tunable photonics device.

Abstract: A semiconductor structure includes a group IV substrate including group IV dies separated by a scribe line. A group IIIV-chiplet is situated over the group IV substrate at least partially over the scribe line. A group III-V process control monitoring device in the group III-V chiplet is situated over the scribe line. Functional group III-V optoelectronic devices can be situated over the group IV dies.

Abstract: A stress-reduced silicon photonics semiconductor wafer includes a silicon nitride layer on a backside of the wafer. At least one silicon nitride stress-reduction configuration is on a topside of the wafer. At least one silicon nitride photonics device is also on the topside of the wafer. A silicon photonics device can be situated in the wafer.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. Precursor stacks having at least one precursor metal are situated over at least one portion of the patterned group III-V device. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over each precursor stack. A filler metal is situated in each contact hole and over each precursor stack. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate. Additional contact holes in the blanket dielectric layer can be situated over the group IV devices and filled with the filler metals.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. A contact metal is situated within the blanket dielectric layer and an interconnect metal is situated over the blanket dielectric layer. The blanket dielectric layer can be substantially planar. The contact metal and the interconnect metal can be electrically connected to the patterned group III-V device. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Abstract: A semiconductor structure includes a group III-V chiplet over a group IV substrate. A group IV optoelectronic device is situated in the group IV substrate. A patterned group III-V optoelectronic device is situated in the group III-V chiplet. A heating element is near the group IV optoelectronic device, or alternatively, near the patterned group III-V optoelectronic device. A dielectric layer is over the patterned group III-V optoelectronic device. A venting hole is in the dielectric layer in proximity of the heating element. A cavity is in the group IV substrate in proximity to the heating element.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: Light detecting structures comprising germanium (Ge) photodiodes formed in a device layer of a germanium on-insulator (GeOI) wafer, focal planes arrays based on such Ge photodiodes (PDs) and methods for fabricating such Ge photodiodes and focal plane arrays (FPAs). An FPA includes a Ge-on-GeOI PD array bonded to a ROIC where the handle layer of the GeOI layer is removed. The GeOI insulator properties and thickness can be designed to improve light coupling into the PDs.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: In fabricating a semiconductor structure, a group IV substrate and a group III-V chiplet are provided. The group III-V chiplet is bonded to the group IV substrate, and patterned to produce a patterned group III-V device. A blanket dielectric layer is formed over the patterned group III-V device. A first contact hole is formed in the blanket dielectric layer over a first portion of the patterned group III-V device. A first liner stack and a first filler metal are subsequently formed in the first contact hole. A second contact hole is formed in the blanket dielectric layer over a second portion of the patterned group III-V device. A second liner stack and a second filler metal are subsequently formed in the second contact hole. A first bottom metal liner of the first liner stack can be different from a second bottom metal liner of the second liner stack.

Abstract: A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.

Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.