Patents by Inventor Edward R. Pillai
Edward R. Pillai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110156730Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.Type: ApplicationFiled: March 4, 2011Publication date: June 30, 2011Inventors: Edward R. Pillai, Erik J. Breiland, Ullrich R. Pfeiffer
-
Patent number: 7956628Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.Type: GrantFiled: November 3, 2006Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Edward R. Pillai, Erik J. Breiland, Ullrich R. Pfeiffer
-
Patent number: 7397261Abstract: A universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.Type: GrantFiled: April 27, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Edward R. Pillai, Joseph Natonio, James D. Rockrohr, David R. Hanson
-
Publication number: 20080106277Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.Type: ApplicationFiled: November 3, 2006Publication date: May 8, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward R. Pillai, Erik J. Breiland, Ullrich R. Pfeiffer
-
Patent number: 7271681Abstract: The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.Type: GrantFiled: July 8, 2005Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventors: Warren D. Dyckman, Gary LaFontant, Edward R. Pillai
-
Patent number: 7265433Abstract: A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.Type: GrantFiled: January 13, 2005Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: Edward R. Pillai, Louis L. Hsu, Wolfgang Sauter, Daniel W. Storaska
-
Patent number: 7085143Abstract: Disclosed is a method and structure for locally powering a semiconductor chip within a package. The structure and method incorporate a local voltage regulator mounted adjacent a semiconductor chip on a top surface of a carrier. The voltage regulator is electrically connected to a power plane disposed within the carrier. The voltage regulator continuously senses the reflected voltage of the power plane at a regulated output port and actively cancels time domain noise within its operational bandwidth. Mounting the voltage regulator on top of the carrier adjacent to the chip minimizes loop inductance between the regulator and power plane and also minimizes delay caused by impedance of the power plane on the current flowing to the chip.Type: GrantFiled: May 23, 2005Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Warren D. Dyckman, Edward R. Pillai, Daniel P. O'Connor
-
Patent number: 6975199Abstract: A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.Type: GrantFiled: December 13, 2001Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: David Clifford Long, Harsaran S. Bhatia, Harvey Charles Hamel, Edward R. Pillai, Christopher David Setzer, Benjamin Paul Tongue
-
Patent number: 6931712Abstract: A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.Type: GrantFiled: January 14, 2004Date of Patent: August 23, 2005Assignee: International Business Machines CorporationInventors: David Clifford Long, Harsaran S. Bhatia, Harvey Charles Hamel, Edward R. Pillai, Christopher David Setzer, Benjamin Paul Tongue
-
Patent number: 6806793Abstract: MLC (multilayer ceramic) frequency selective circuit structures are disclosed. The MLC frequency selective circuit structures have a solenoid and toroid coil geometry in a multilayer electronic package which functions as a frequency selective tuned circuit in which both the number of turns and the aspect ratio of the solenoid coil are selected to adjust the tuned frequency. In some embodiments, a plurality of such coils can be connected together to provide a selected bandwidth about a tuned center frequency.Type: GrantFiled: December 13, 2002Date of Patent: October 19, 2004Assignee: International Business Machines CorporationInventors: Harsaran S. Bhatia, Harvey C. Hamel, David C. Long, Edward R. Pillai, Christopher D. Setzer, Benjamin P. Tongue
-
Publication number: 20040113721Abstract: MLC (multilayer ceramic) frequency selective circuit structures are disclosed. The MLC frequency selective circuit structures have a solenoid and toroid coil geometry in a multilayer electronic package which functions as a frequency selective tuned circuit in which both the number of turns and the aspect ratio of the solenoid coil are selected to adjust the tuned frequency. In some embodiments, a plurality of such coils can be connected together to provide a selected bandwidth about a tuned center frequency.Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harsaran S. Bhatia, Harvey C. Hamel, David C. Long, Edward R. Pillai, Christopher D. Setzer, Benjamin P. Tongue
-
Patent number: 6680530Abstract: In packaging integrated circuits for high speed (multi-gigabit) applications, chip carriers having signal paths between the substrate board and the chips at the top with a number of evenly divided vertical steps produces frequency properties that are sufficiently good that it is possible to run signals through the package, rather than by means of connectors attached to the top surface of the carrier.Type: GrantFiled: August 12, 2002Date of Patent: January 20, 2004Assignee: International Business Machines CorporationInventors: Edward R. Pillai, Warren D. Dyckman
-
Patent number: 6657864Abstract: A high power density thermal packaging solution. A highly efficient thermal path is provided using a lid of a unique design configuration that connects the chip back-side to both a heat sink and thermally conductive substrate vias thus establishing two thermal paths to carry heat from the die. The thermal interface between the chip back-side to lid and lid-to-substrate is enhanced with a thermally conductive elastomer. The heat is conducted through the substrate through thermal vias that are added to the perimeter of the substrate or which may be configured from preexisting electrical shielding structures that connect the top surface of the substrate to the bottom of the package. The bottom surface connection then conducts the heat to a copper ground plane in the printed circuit card. The heat from the die to the heat sink is transferred in the conventional method using the thin layer of thermally conductive elastomer to complete the thermal path from chip to lid to heat sink.Type: GrantFiled: December 16, 2002Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Warren D. Dyckman, Edward R. Pillai, Jeffrey A. Zitz
-
Patent number: 6583498Abstract: In a package for integrated circuits, a signal transmission line has a first segment closer to the chip that is bracketed vertically by ground planes at a first vertical distance and a second segment further from the chip that is bracketed vertically by ground planes at a second vertical distance greater than the first distance, with an aperture being formed in the ground planes at the first distance, so that those ground planes do not interfere with the impedance set by the second set of ground planes.Type: GrantFiled: August 9, 2002Date of Patent: June 24, 2003Assignee: International Business Machine CorporationInventors: Edward R. Pillai, Warren D. Dyckman, Deana Cosmadelis
-
Publication number: 20030112114Abstract: A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.Type: ApplicationFiled: December 13, 2001Publication date: June 19, 2003Applicant: International Business Machines CorporationInventors: David Clifford Long, Harsaran S. Bhatia, Harvey Charles Hamel, Edward R. Pillai, Christopher David Setzer, Benjamin Paul Tongue
-
Patent number: 6501174Abstract: A semiconductor interconnect connection mechanism for attaching individual surface mounted semiconductor objects to multichip products whereby at least a portion of the electrical pathway between different objects on the top surface of surface mounted devices is not located on the top surface.Type: GrantFiled: January 17, 2001Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: Krystyna W. Semkow, Edward R. Pillai, Linda L. Rapp
-
Publication number: 20020130410Abstract: A semiconductor interconnecting mechanism, havingType: ApplicationFiled: January 17, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: Krystyna W. Semkow, Edward R. Pillai, Linda L. Rapp