Abstract: A digital circuit (11) for compelling storage of attributes and for providing output signals indicating status of the storage of attributes, the digital circuit comprising: a digital storage device (26); a first combinational logic circuit (20) connected to the digital storage device (26) for enabling the digital storage device (26) to store the attributes based upon a set of stable first compelled inputs and an enable signal; a second combinational logic circuit (18) connected to the digital storage device for clearing the digital storage device (26) based upon a set of stable second compelled inputs and a clear signal; a first logic gate (30) connected to the digital storage device (26) and the first combinational logic circuit (20) for outputting a signal representative of the attribute being stored in the digital storage device (26); and a second logic gate (28) connected to the digital storage device (26) and the second combinational logic circuit (18) for outputting a signal representative of the digita

Abstract: A method of improving efficiency in computer systems through a novel arbitration scheme is disclosed. The arbitration scheme includes a bus arbiter circuit that transparently operates in both central arbitration and distributed arbitration computer systems. The bus arbiter circuit includes an arbitration request sequencer, an arbitration competition protocol sequencer, a multiplexer, a latch, two comparators, and a series of control status registers that together provide increased system efficiency by effectively self-preempting competition priorities on its own board, thus allowing tasks with the highest priorities to compete for mastership of the bus and eliminating priority inversions.

Abstract: A method and apparatus for a time domain boundary bridge circuit for capturing an event on an asynchronous input is described, comprising an S-R latch coupled to an asynchronous input, a first D flip-flop coupled to a synchronous clock and the output of the S-R latch, and a second D type flip-flop coupled to a synchronous clock and the output of the first D flip-flop, and having an output coupled to a circuit output terminal, operable to provide a synchronous output which reflects an event occurrence on the asynchronous input.

Abstract: A method and apparatus for a circuit physically realizing a time domain boundary buffer circuit for coupling an asynchronous sequential state machine controller to an asynchronous bus interface is described. A time domain boundary bridge latch circuit comprising a latch coupled to an asynchronous input, a delay element, and further coupled to a signal from the asynchronous sequential machine so that the signal from the asynchronous bus may be reliably captured is coupled to an input of the asynchronous sequential machine. The circuitry is designed to enable the asynchronous sequential machine to sample the asynchronous input as rapidly as possible without metastability errors. A second embodiment is disclosed for coupling an asynchronous sequential machine to a plurality of data bits on an asynchronous bus interface. Additional embodiments and applications are also disclosed.

Abstract: One embodiment of the present invention is a digital circuit (10) for providing glitch-free data in an asynchronous environment, the circuit comprising: an input circuit (11) for accepting data; combinational logic circuitry (12) for accepting the data from the input circuit (11 ) and manipulating the data to provide output data, wherein a delay in data flow occurs while the combinational logic manipulates the data; and an output circuit (14) for accepting the output data at a predetermined period after the receipt of data by the input circuit. Preferably, the predetermined period is at least as long as the delay in data flow.

Abstract: A method and apparatus for a circuit physically realizing a time domain boundary buffer circuit for capturing data signals transmitted on an asynchronous domain bus and transmitting the data signals to a synchronous domain is described. The circuit comprises a data ready circuit and a data buffer circuit. The data ready circuit comprises a first flip flop is coupled to an asynchronous input, a second flip-flop is coupled to the synchronous domain clock and the output of the first flip flop, and a third flip-flop is coupled to the synchronous domain clock and the output of the second flip-flop, the circuit having an output coupled to a circuit output terminal; the third flip flop for providing a synchronous output which reflects an event occurrence on the asynchronous input. Other embodiments are also described.