Patents by Inventor Edward R. Van Brunt

Edward R. Van Brunt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998418
    Abstract: Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 4, 2021
    Assignee: CREE, INC.
    Inventors: Edward R. Van Brunt, Daniel J. Lichtenwalner, Shadi Sabri
  • Publication number: 20210098568
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Application
    Filed: November 19, 2020
    Publication date: April 1, 2021
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Patent number: 10861931
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: December 8, 2020
    Assignee: Cree, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Publication number: 20200365708
    Abstract: Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Edward R. Van Brunt, Daniel J. Lichtenwalner, Shadi Sabri
  • Patent number: 10510905
    Abstract: A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 17, 2019
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Edward R. Van Brunt, Brett Hull, Scott Thomas Allen
  • Publication number: 20190013416
    Abstract: A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Qingchun Zhang, Edward R. Van Brunt, Brett Hull, Scott Thomas Allen
  • Publication number: 20180166530
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Application
    Filed: December 8, 2016
    Publication date: June 14, 2018
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Patent number: 9887287
    Abstract: Semiconductor devices include a semiconductor layer structure having a wide band-gap semiconductor drift region having a first conductivity type. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having first and second opposed sidewalls that extend in a first direction in the upper portion of the semiconductor layer structure. These devices further include a deep shielding pattern having a second conductivity type that is opposite the first conductivity type in the semiconductor layer structure underneath a bottom surface of the gate trench, and a deep shielding connection pattern that has the second conductivity type in the first sidewall of the gate trench. The devices include a semiconductor channel region that has the first conductivity type in the second sidewall of the gate trench.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 6, 2018
    Assignee: Cree, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull, Alexander V. Suvorov, Craig Capell